Inventor · disambiguated record
Christopher S. Blair
Also filed as: BLAIR CHRISTOPHER S · BLAIR CHRISTOPHER SCOTT
20 granted patents·571 citations·filing 1990–2013
96Inventor score
Top patents by PatentIndex Score
20 records- 0191US9673316B1Vertical semiconductor device having frontside interconnectionsMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted Jun 6, 2017·9 cites·8 claims
- 0291US5338696AMethod of fabricating BiCMOS deviceNAT SEMICONDUCTOR CORP·Filed 1993·Granted Aug 16, 1994·79 cites·8 claims
- 0390US6136705ASelf-aligned dual thickness cobalt silicide layer formation processNAT SEMICONDUCTOR CORP·Filed 1998·Granted Oct 24, 2000·89 cites·13 claims
- 0489US5998873ALow contact resistance and low junction leakage metal interconnect contact structureNAT SEMICONDUCTOR CORP·Filed 1998·Granted Dec 7, 1999·109 cites·9 claims
- 0581US6103610AIntegrated circuit structure with dual thickness cobalt silicide layers and method for its manufactureNAT SEMICONDUCTOR CORP·Filed 1999·Granted Aug 15, 2000·41 cites·12 claims
- 0679US6040606AIntegrated circuit structure with dual thickness cobalt silicide layers and method for its manufactureNAT SEMICONDUCTOR CORP·Filed 1998·Granted Mar 21, 2000·36 cites·3 claims
- 0777US9209091B1Integrated monolithic galvanic isolatorHARPER DAVID·Filed 2011·Granted Dec 8, 2015·5 cites·6 claims
- 0871US8624349B1Simultaneous isolation trench and handle wafer contact formationBLAIR CHRISTOPHER S·Filed 2010·Granted Jan 7, 2014·4 cites·9 claims
- 0970US5661046AMethod of fabricating BiCMOS deviceNAT SEMICONDUCTOR CORP·Filed 1994·Granted Aug 26, 1997·24 cites·4 claims
- 1067US6171901B1Process for forming silicided capacitor utilizing oxidation barrier layerNAT SEMICONDUCTOR CORP·Filed 1999·Granted Jan 9, 2001·33 cites·20 claims
- 1163US8963281B1Simultaneous isolation trench and handle wafer contact formationMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted Feb 24, 2015·1 cites·3 claims
- 1262US6303503B1Process for the formation of cobalt salicide layers employing a sputter etch surface preparation stepNAT SEMICONDUCTOR CORP·Filed 1999·Granted Oct 16, 2001·25 cites·21 claims
- 1357US5338694AMethod of fabricating BiCMOS deviceNAT SEMICONDUCTOR CORP·Filed 1992·Granted Aug 16, 1994·15 cites·1 claims
- 1453US5451546AMasking method used in salicide process for improved yield by preventing damage to oxide spacersNAT SEMICONDUCTOR CORP·Filed 1994·Granted Sep 19, 1995·22 cites·9 claims
- 1551US5882976AMethod of fabricating a self-aligned double polysilicon NPN transistor with poly etch stopNAT SEMICONDUCTOR CORP·Filed 1997·Granted Mar 16, 1999·13 cites·13 claims
- 1651US5139961AReducing base resistance of a bjt by forming a self aligned silicide in the single crystal region of the extrinsic baseNAT SEMICONDUCTOR CORP·Filed 1990·Granted Aug 18, 1992·25 cites·13 claims
- 1751US5045483ASelf-aligned silicided base bipolar transistor and resistor and method of fabricationNAT SEMICONDUCTOR CORP·Filed 1990·Granted Sep 3, 1991·17 cites·5 claims
- 1845US5904536ASelf aligned poly emitter bipolar technology using damascene techniqueNAT SEMICONDUCTOR CORP·Filed 1998·Granted May 18, 1999·9 cites·16 claims
- 1941US5925923AMerged single polysilicon bipolar NPN transistorNAT SEMICONDUCTOR CORP·Filed 1997·Granted Jul 20, 1999·7 cites·2 claims
- 2036US5242854AHigh performance semiconductor devices and their manufactureNAT SEMICONDUCTOR CORP·Filed 1992·Granted Sep 7, 1993·8 cites·9 claims
Join the waitlist — get patent alerts
Get an alert when Christopher S. Blair files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →