Inventor · disambiguated record
Chao-Chiang Chen
Also filed as: CHEN CHAO CHIANG
8 granted patents·2 pending applications·705 citations·filing 1993–2015
91Inventor score
Files withALTERA CORP5AGATE LOGIC INC1CHAN KAI KEUNG1CHEN CHAO-CHIANG1INTELLIGENT LOGIC SYSTEMS INC1
Top patents by PatentIndex Score
10 records- 0196US6353552B2PLD with on-chip memory having a shadow registerALTERA CORP·Filed 2001·Granted Mar 5, 2002·56 cites·54 claims
- 0294US6011744AProgrammable logic device with multi-port memoryALTERA CORP·Filed 1997·Granted Jan 4, 2000·69 cites·11 claims
- 0393US6317367B1FPGA with on-chip multiport memoryALTERA CORP·Filed 2000·Granted Nov 13, 2001·37 cites·128 claims
- 0492US5455525AHierarchically-structured programmable logic array and system for interconnecting logic elements in the logic arrayINTELLIGENT LOGIC SYSTEMS INC·Filed 1993·Granted Oct 3, 1995·488 cites·30 claims
- 0584US8981813B2Method and apparatus for facilitating communication between programmable logic circuit and application specific integrated circuit with clock adjustmentAGATE LOGIC INC·Filed 2012·Granted Mar 17, 2015·8 cites·18 claims
- 0682US6011730AProgrammable logic device with multi-port memoryALTERA CORP·Filed 1999·Granted Jan 4, 2000·31 cites·42 claims
- 0769US6151258AProgrammable logic device with multi-port memoryQUICKTURN DESIGN SYSTEMS INC·Filed 1999·Granted Nov 21, 2000·13 cites·18 claims
- 0843US2007234266A1Method of optimizing IC logic performance by static timing based parasitic budgetingCHEN CHAO-CHIANG·Filed 2004·Application pending·0 cites
- 0941US6219284B1Programmable logic device with multi-port memoryALTERA CORP·Filed 1999·Granted Apr 17, 2001·3 cites·7 claims
- 1028US2018062654A9Method and apparatus for facilitating communication between programmable logic circuit and application specific integrated circuit with clock adjustmentCHAN KAI KEUNG·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →