Inventor · disambiguated record
Chen-Fu Chien
Also filed as: CHIEN CHEN-FU
10 granted patents·6 pending applications·75 citations·filing 2000–2018
86Inventor score
Files withNAT UNIV TSING HUA7MACRONIX INT CO LTD4CHIEN CHEN-FU2CHEN FU CHIEN1TAIWAN SEMICONDUCTOR MFG1
Top patents by PatentIndex Score
16 records- 0184US7586609B2Method for analyzing overlay errorsMACRONIX INT CO LTD·Filed 2005·Granted Sep 8, 2009·9 cites·11 claims
- 0282US7353077B2Methods for optimizing die placementTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Apr 1, 2008·13 cites·21 claims
- 0377US6975974B2Overlay error model, sampling strategy and associated equipment for implementationMACRONIX INT CO LTD·Filed 2001·Granted Dec 13, 2005·26 cites·5 claims
- 0474US6368761B1Procedure of alignment for optimal wafer exposure patternMACRONIX INT CO LTD·Filed 2000·Granted Apr 9, 2002·16 cites·47 claims
- 0573US8200528B2Factor analysis system and analysis method thereofCHIEN CHEN-FU·Filed 2010·Granted Jun 12, 2012·7 cites·10 claims
- 0656US9082009B2Method of defect image classification through integrating image analysis and data miningNAT UNIV TSING HUA·Filed 2014·Granted Jul 14, 2015·1 cites·9 claims
- 0755US9563857B2Multi-objective semiconductor product capacity planning system and method thereofNAT UNIV TSING HUA·Filed 2014·Granted Feb 7, 2017·3 cites·8 claims
- 0852US2015051936A1Resource planning system and method for classification productsNAT UNIV TSING HUA·Filed 2013·Application pending·0 cites
- 0944US2016048628A1Method for dynamic experimental designNAT UNIV TSING HUA·Filed 2014·Application pending·0 cites
- 1044US2019197569A1Optimization method and system of matching product experiencing activity with participantsUNIV NAT TSING HUA·Filed 2018·Application pending·0 cites
- 1144US2003110102A1Method for goods arrangement and its systemCHEN FU CHIEN·Filed 2001·Application pending·0 cites
- 1243US9513626B2Method of dispatching semiconductor batch productionNAT UNIV TSING HUA·Filed 2014·Granted Dec 6, 2016·0 cites·5 claims
- 1340US2015051859A1Analytic system of wafer bin map and non-transitory computer readable media thereofNAT UNIV TSING HUA·Filed 2013·Application pending·0 cites
- 1437US8863047B1Photolithography capacity planning system and non-transitory computer readable media thereofNAT UNIV TSING HUA·Filed 2013·Granted Oct 14, 2014·0 cites·16 claims
- 1535US8407631B2Method for enhancing wafer exposure effectiveness and efficiencyCHIEN CHEN-FU·Filed 2010·Granted Mar 26, 2013·0 cites·7 claims
- 1631US2005003617A1Template padding method for padding edges of holes on semiconductor masksMACRONIX INT CO LTD·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →