Inventor · disambiguated record
Chee Keong Chin
Also filed as: CHIN CHEE KEONG
17 granted patents·2 pending applications·94 citations·filing 2006–2022
91Inventor score
Files withCHIN CHEE KEONG8SANDISK SEMICONDUCTOR SHANGHAI CO LTD4SANDISK TECHNOLOGIES INC2STATS CHIPPAC LTD2WESTERN DIGITAL TECH INC2
Top patents by PatentIndex Score
19 records- 0194US8138017B2Integrated circuit package system with through semiconductor vias and method of manufacture thereofCHIN CHEE KEONG·Filed 2010·Granted Mar 20, 2012·24 cites·17 claims
- 0290US7867821B1Integrated circuit package system with through semiconductor vias and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Jan 11, 2011·19 cites·17 claims
- 0386US8037918B2Pick-up heads and systems for die bonding and related applicationsSTATS CHIPPAC INC·Filed 2006·Granted Oct 18, 2011·17 cites·16 claims
- 0483US8541886B2Integrated circuit packaging system with via and method of manufacture thereofCHIN CHEE KEONG·Filed 2010·Granted Sep 24, 2013·8 cites·11 claims
- 0581US10483239B2Semiconductor device including dual pad wire bond interconnectionSANDISK SEMICONDUCTOR SHANGHAI CO LTD·Filed 2018·Granted Nov 19, 2019·5 cites·22 claims
- 0675US10418334B2Semiconductor device including corner recessSANDISK SEMICONDUCTOR SHANGHAI CO LTD·Filed 2017·Granted Sep 17, 2019·2 cites·16 claims
- 0775US8242607B2Integrated circuit package system with offset stacked die and method of manufacture thereofCHIN CHEE KEONG·Filed 2007·Granted Aug 14, 2012·7 cites·19 claims
- 0875US7989941B2Integrated circuit package system with support structure for die overhangSTATS CHIPPAC LTD·Filed 2008·Granted Aug 2, 2011·8 cites·20 claims
- 0961US8946878B2Integrated circuit package-in-package system housing a plurality of stacked and offset integrated circuits and method of manufacture thereforCHIN CHEE KEONG·Filed 2007·Granted Feb 3, 2015·4 cites·9 claims
- 1055US12463097B2Semiconductor device with reduced stress die pick and placeSANDISK TECHNOLOGIES INC·Filed 2021·Granted Nov 4, 2025·0 cites·12 claims
- 1155US11289395B2Aperture structure on semiconductor component backside to alleviate delamination in stacked packagingWESTERN DIGITAL TECH INC·Filed 2020·Granted Mar 29, 2022·0 cites·8 claims
- 1250US11177241B2Semiconductor device with top die positioned to reduce die crackingWESTERN DIGITAL TECH INC·Filed 2020·Granted Nov 16, 2021·0 cites·20 claims
- 1349US12506036B2Dicing and wafer thinning to form semiconductor diesSANDISK TECHNOLOGIES INC·Filed 2022·Granted Dec 23, 2025·0 cites·7 claims
- 1445US2007284139A1Sawn integrated circuit package systemCHIN CHEE KEONG·Filed 2007·Application pending·0 cites
- 1544US8901439B2Integrated circuit package system with window openingCHIN CHEE KEONG·Filed 2006·Granted Dec 2, 2014·0 cites·20 claims
- 1642US10128218B2Semiconductor device including die bond pads at a die edgeSANDISK SEMICONDUCTOR SHANGHAI CO LTD·Filed 2017·Granted Nov 13, 2018·0 cites·24 claims
- 1742US2008237157A1Wafer transport systemCHIN CHEE KEONG·Filed 2007·Application pending·0 cites
- 1841US8288860B2Memory device system with stacked packagesCHIN CHEE KEONG·Filed 2008·Granted Oct 16, 2012·0 cites·20 claims
- 1938US10283485B2Semiconductor device including conductive bump interconnectionsSANDISK SEMICONDUCTOR SHANGHAI CO LTD·Filed 2017·Granted May 7, 2019·0 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →