Inventor · disambiguated record

Choon-Hun Choo

Also filed as: CHOO CHOON-HUN

1 granted patent·56 citations·filing 2012–2012

49Inventor score

Technology areasH03K

Files withEASIC CORP1

Top patents by PatentIndex Score

1 record

0193US8629548B1Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic nodeEASIC CORP·Filed 2012·Granted Jan 14, 2014·56 cites·20 claims

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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →