Inventor · disambiguated record
Chien-Chun Chou
Also filed as: CHOU CHIEN-CHUN
34 granted patents·3 pending applications·312 citations·filing 2002–2025
97Inventor score
Files withSONICS INC13MARVELL ASIA PTE LTD10SRINIVASAN KRISHNAN5WINGARD DREW E4ALEXANIAN HERVE JACQUES2
Top patents by PatentIndex Score
37 records- 0194US11467811B1Method and apparatus for generating metadata by a compilerMARVELL ASIA PTE LTD·Filed 2021·Granted Oct 11, 2022·4 cites·32 claims
- 0294US10062422B2Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targetsSONICS INC·Filed 2016·Granted Aug 28, 2018·7 cites·20 claims
- 0392US12174727B1Method and apparatus for correlating high-level code with low-level instructions for machine learning applicationsMARVELL ASIA PTE LTD·Filed 2021·Granted Dec 24, 2024·3 cites·29 claims
- 0489US12190086B1Method and apparatus for ML graphs by a compilerMARVELL ASIA PTE LTD·Filed 2022·Granted Jan 7, 2025·3 cites·20 claims
- 0589US8108648B2Various methods and apparatus for address tilingSRINIVASAN KRISHNAN·Filed 2009·Granted Jan 31, 2012·25 cites·22 claims
- 0687US11977475B1Method and apparatus for compiler and low-level instruction validation of machine learning operations on hardwareMARVELL ASIA PTE LTD·Filed 2022·Granted May 7, 2024·2 cites·34 claims
- 0786US12443399B1Method and system for code optimization based on statistical dataMARVELL ASIA PTE LTD·Filed 2023·Granted Oct 14, 2025·1 cites·34 claims
- 0885US12293174B1Method and system for memory management within machine learning inference engineMARVELL ASIA PTE LTD·Filed 2023·Granted May 6, 2025·2 cites·58 claims
- 0985US8020124B2Various methods and apparatuses for cycle accurate C-models of componentsSONICS INC·Filed 2008·Granted Sep 13, 2011·19 cites·15 claims
- 1084US9292436B2Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundaryWINGARD DREW E·Filed 2008·Granted Mar 22, 2016·10 cites·20 claims
- 1183US11995448B1Method and apparatus for performing machine learning operations in parallel on machine learning hardwareMARVELL ASIA PTE LTD·Filed 2021·Granted May 28, 2024·1 cites·36 claims
- 1283US8407433B2Interconnect implementing internal controlsWINGARD DREW E·Filed 2008·Granted Mar 26, 2013·9 cites·21 claims
- 1383US8032329B2Method and system to monitor, debug, and analyze performance of an electronic designSONICS INC·Filed 2008·Granted Oct 4, 2011·14 cites·25 claims
- 1483US6976106B2Method and apparatus for speculative response arbitration to improve system latencySONICS INC·Filed 2002·Granted Dec 13, 2005·37 cites·17 claims
- 1582US9495290B2Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction orderingWINGARD DREW E·Filed 2008·Granted Nov 15, 2016·8 cites·20 claims
- 1681US8972995B2Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threadsSRINIVASAN KRISHNAN·Filed 2010·Granted Mar 3, 2015·11 cites·19 claims
- 1780US2025383850A1Multistage compiler architectureMARVELL ASIA PTE LTD·Filed 2025·Application pending·0 cites
- 1879US8438320B2Various methods and apparatus for address tiling and channel interleaving throughout the integrated systemSRINIVASAN KRISHNAN·Filed 2009·Granted May 7, 2013·9 cites·20 claims
- 1978US7356633B2Composing on-chip interconnects with configurable interfacesSONICS INC·Filed 2002·Granted Apr 8, 2008·22 cites·42 claims
- 2077US7254603B2On-chip inter-network performance optimization using configurable performance parametersSONICS INC·Filed 2002·Granted Aug 7, 2007·26 cites·22 claims
- 2175US8073820B2Method and system for a database to monitor and analyze performance of an electronic designSRINIVASAN KRISHNAN·Filed 2008·Granted Dec 6, 2011·9 cites·18 claims
- 2274US10303628B2Reordering responses in a high performance on-chip networkSONICS INC·Filed 2015·Granted May 28, 2019·2 cites·18 claims
- 2373US8229723B2Performance software instrumentation and analysis for electronic design automationSRINIVASAN KRISHNAN·Filed 2007·Granted Jul 24, 2012·7 cites·20 claims
- 2472US7266786B2Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systemsSONICS INC·Filed 2002·Granted Sep 4, 2007·15 cites·41 claims
- 2571US11733983B2Method and apparatus for generating metadata by a compilerMARVELL ASIA PTE LTD·Filed 2022·Granted Aug 22, 2023·0 cites·26 claims
- 2671US10664421B1Reordering responses in a high performance on-chip networkFACEBOOK TECH LLC·Filed 2019·Granted May 26, 2020·1 cites·19 claims
- 2771US7660932B2Composing on-chip interconnects with configurable interfacesSONICS INC·Filed 2008·Granted Feb 9, 2010·4 cites·8 claims
- 2871US7194566B2Communication system and method with configurable posting pointsSONICS INC·Filed 2002·Granted Mar 20, 2007·16 cites·63 claims
- 2966US8504992B2Method and apparatus for establishing a quality of service modelWEBER WOLF-DIETRICH·Filed 2010·Granted Aug 6, 2013·2 cites·20 claims
- 3066US7302691B2Scalable low bandwidth multicast handling in mixed core systemsSONICS INC·Filed 2002·Granted Nov 27, 2007·11 cites·38 claims
- 3165US7603441B2Method and apparatus for automatic configuration of multiple on-chip interconnectsSONICS INC·Filed 2002·Granted Oct 13, 2009·11 cites·27 claims
- 3264US7243264B2Method and apparatus for error handling in networksSONICS INC·Filed 2002·Granted Jul 10, 2007·10 cites·24 claims
- 3363US12430108B2Multistage compiler architectureMARVELL ASIA PTE LTD·Filed 2022·Granted Sep 30, 2025·0 cites·40 claims
- 3461US9087036B1Methods and apparatuses for time annotated transaction level modelingCHOU CHIEN-CHUN·Filed 2005·Granted Jul 21, 2015·7 cites·20 claims
- 3560US8868397B2Transaction co-validation across abstraction layersALEXANIAN HERVE JACQUES·Filed 2007·Granted Oct 21, 2014·4 cites·11 claims
- 3652US2012036296A1Interconnect that eliminates routing congestion and manages simultaneous transactionsWINGARD DREW E·Filed 2011·Application pending·0 cites
- 3737US2008120082A1Transaction Co-Validation Across Abstraction LayersALEXANIAN HERVE JACQUES·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →