Inventor · disambiguated record
Chia-Chi Chu
Also filed as: CHU CHIA-CHI
20 granted patents·8 pending applications·229 citations·filing 2004–2015
94Inventor score
Top patents by PatentIndex Score
28 records- 0189US7321834B2Method for calculating power flow solution of a power transmission network that includes interline power flow controller (IPFC)UNIV CHANG GUNG·Filed 2005·Granted Jan 22, 2008·45 cites·8 claims
- 0289US7177727B2Method for calculating power flow solution of a power transmission network that includes unified power flow controllersUNIV CHANG GUNG·Filed 2005·Granted Feb 13, 2007·47 cites·17 claims
- 0388US7813884B2Method of calculating power flow solution of a power grid that includes generalized power flow controllersUNIV CHANG GUNG·Filed 2008·Granted Oct 12, 2010·29 cites·6 claims
- 0477US7191418B2Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integrationUNIV CHANG GUNG·Filed 2004·Granted Mar 13, 2007·25 cites·3 claims
- 0573US7216322B2Clock tree synthesis for low power consumption and low clock skewUNIV CHANG GUNG·Filed 2004·Granted May 8, 2007·20 cites·3 claims
- 0671US9906033B2Consensus-based power control apparatusUNIV NAT TSING HUA·Filed 2015·Granted Feb 27, 2018·2 cites·11 claims
- 0768US7181664B2Method on scan chain reordering for lowering VLSI power consumptionUNIV CHANG GUNG·Filed 2004·Granted Feb 20, 2007·14 cites·6 claims
- 0866US7562324B2Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimizationUNIV CHANG GUNG·Filed 2006·Granted Jul 14, 2009·4 cites·3 claims
- 0964US7600206B2Method of estimating the signal delay in a VLSI circuitUNIV CHANG GUNG·Filed 2007·Granted Oct 6, 2009·4 cites·4 claims
- 1060US7254790B2Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loopsUNIV CHANG GUNG·Filed 2004·Granted Aug 7, 2007·8 cites·3 claims
- 1159US7398499B2Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit designUNIV CHANG GUNG·Filed 2006·Granted Jul 8, 2008·2 cites·6 claims
- 1258US7216309B2Method and apparatus for model-order reduction and sensitivity analysisUNIV CHANG GUNG·Filed 2004·Granted May 8, 2007·6 cites·9 claims
- 1358US7017130B2Method of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuitsUNIV CHANG GUNG·Filed 2004·Granted Mar 21, 2006·7 cites·2 claims
- 1457US7124381B2Method of estimating crosstalk noise in lumped RLC coupled interconnectsUNIV CHANG GUNG·Filed 2004·Granted Oct 17, 2006·7 cites·4 claims
- 1550US7797140B2Generalizations of adjoint networks techniques for RLC interconnects model-order reductionsUNIV CHANG GUNG·Filed 2004·Granted Sep 14, 2010·2 cites·2 claims
- 1649US8060349B2Method of designing a static synchronous compensator based on passivity-based controlCHU CHIA-CHI·Filed 2007·Granted Nov 15, 2011·4 cites·6 claims
- 1746US2006282239A1Method of setting-up steady state model of VSC-based multi-terminal HVDC transmission systemUNIV CHANG GUNG·Filed 2005·Application pending·0 cites
- 1845US7373367B2Efficient digital filter design tool for approximating an FIR filter with a low-order linear-phase IIR filterUNIV CHANG GUNG·Filed 2004·Granted May 13, 2008·3 cites·1 claims
- 1945US2006100830A1Moment computations of nonuniform distributed coupled RLC trees with applications to estimating crosstalk noiseUNIV CHANG GUNG·Filed 2004·Application pending·0 cites
- 2045US2015051856A1Method for estimating voltage stabilityNAT UNIV TSING HUA·Filed 2013·Application pending·0 cites
- 2143US7512525B2Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive ordersUNIV CHANG GUNG·Filed 2005·Granted Mar 31, 2009·0 cites·8 claims
- 2243US2008126028A1Method of reducing a multiple-inputs multiple-outputs (MIMO) interconnect circuit system in a global lanczos algorithmUNIV CHANG GUNG·Filed 2006·Application pending·0 cites
- 2342US7437689B2Interconnect model-order reduction methodUNIV CHANG GUNG·Filed 2005·Granted Oct 14, 2008·0 cites·4 claims
- 2442US2015051866A1Method for optimizing phasor measurement unit placementNAT UNIV TSING HUA·Filed 2013·Application pending·0 cites
- 2542US2007255538A1Method of developing an analogical VLSI macro model in a global Arnoldi algorithmUNIV CHANG GUNG·Filed 2006·Application pending·0 cites
- 2641US7509243B2Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithmUNIV CHANG GUNG·Filed 2005·Granted Mar 24, 2009·0 cites·2 claims
- 2739US2006047370A1Efficient look-ahead load margin and voltage profiles contingency analysis using a tangent vector index methodUNIV CHANG GUNG·Filed 2004·Application pending·0 cites
- 2839US2008282215A1Method of designing a digital integrated circuit for a multi-functional digital protective relayCHU CHIA-CHI·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →