Inventor · disambiguated record
Chia-Chi Chung
Also filed as: CHUNG CHIA-CHI
17 granted patents·10 pending applications·117 citations·filing 2001–2025
92Inventor score
Files withMACRONIX INT CO LTD7TAIWAN SEMICONDUCTOR MFG CO LTD7CORETRONIC CORP4TAIWAN SEMICONDUCTOR MFG3CHENG CHUNG-HSIU1
Top patents by PatentIndex Score
27 records- 0187US10295909B2Edge-exposure tool with an ultraviolet (UV) light emitting diode (LED)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted May 21, 2019·5 cites·20 claims
- 0285US6774051B2Method for reducing pitchMACRONIX INT CO LTD·Filed 2002·Granted Aug 10, 2004·36 cites·24 claims
- 0377US7026682B2Non-volatile memory device with enlarged trapping layerMACRONIX INT CO LTD·Filed 2004·Granted Apr 11, 2006·32 cites·6 claims
- 0474US10155305B2Multi-function multi-angle cleaning toolTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 18, 2018·3 cites·20 claims
- 0573US10964653B2Method of forming a semiconductor device comprising top conductive padsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Mar 30, 2021·3 cites·19 claims
- 0668US2024387312A1Silicon fragment defect reduction in grinding processTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0762US10739682B2Edge-exposure tool with an ultraviolet (UV) light emitting diode (LED)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Aug 11, 2020·0 cites·20 claims
- 0862US6670275B2Method of rounding a topcorner of trenchMACRONIX INT CO LTD·Filed 2002·Granted Dec 30, 2003·10 cites·2 claims
- 0961US6790772B2Dual damascene processing method using silicon rich oxide layer thereof and its structureMACRONIX INT CO LTD·Filed 2002·Granted Sep 14, 2004·11 cites·20 claims
- 1060US8124537B2Method for etching integrated circuit structureLEE CHUN-HUNG·Filed 2008·Granted Feb 28, 2012·1 cites·20 claims
- 1159US10509323B2Edge-exposure tool with an ultraviolet (UV) light emitting diode (LED)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 17, 2019·0 cites·20 claims
- 1259US6791190B1Self-aligned contact/borderless contact opening and method for forming sameMACRONIX INT CO LTD·Filed 2003·Granted Sep 14, 2004·9 cites·16 claims
- 1357US2025271731A1Projection lens module and projection deviceCORETRONIC CORP·Filed 2025·Application pending·0 cites
- 1455US2023400756A1Projection apparatus and calibration methodCORETRONIC CORP·Filed 2023·Application pending·0 cites
- 1551US7993018B2Projection optical system and light amount adjusting component used in the sameCORETRONIC CORP·Filed 2009·Granted Aug 9, 2011·0 cites·20 claims
- 1650US8673788B2Method of forming a layer on a semiconductor substrate having a plurality of trenchesCHENG CHUNG-HSIU·Filed 2010·Granted Mar 18, 2014·1 cites·16 claims
- 1747US10131539B2Method for forming micro-electro-mechanical system (MEMS) device structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Nov 20, 2018·0 cites·20 claims
- 1845US6713332B2Non-volatile memory device with enlarged trapping layerMACRONIX INT CO LTD·Filed 2002·Granted Mar 30, 2004·6 cites·21 claims
- 1943US2022308428A1Projection apparatus and calibration methodCORETRONIC CORP·Filed 2022·Application pending·0 cites
- 2042US2009035902A1Integrated method of fabricating a memory device with reduced pitchTAIWAN SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 2141US9720312B2Projection screen and manufacturing method of projection screenSU FANG-HSUAN·Filed 2014·Granted Aug 1, 2017·0 cites·8 claims
- 2240US2008174027A1Semiconductor interconnect structure with rounded edges and method for forming the sameTAIWAN SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 2339US8523396B2Device housingCHUNG CHIA-CHI·Filed 2011·Granted Sep 3, 2013·0 cites·10 claims
- 2439US2006286792A1Dual damascene processTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 2535US2003157795A1Self-aligned patterning in dual damascene processMACRONIX INT CO LTD·Filed 2002·Application pending·0 cites
- 2632US2003057184A1Method for pull back SiN to increase rounding effect in a shallow trench isolation processFiled 2001·Application pending·0 cites
- 2731US2002009893A1Method of forming a conductor in a fluoride silicate glass (FSG) layerFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →