Inventor · disambiguated record
Chia-Ming Ho
Also filed as: HO CHIA-MING
16 granted patents·976 citations·filing 2003–2017
94Inventor score
Files withTAIWAN SEMICONDUCTOR MFG6TAIWAN SEMICONDUCTOR MFG CO LTD5SU KE-YING2HO CHIA-MING1UNIV CHANG GUNG1
Top patents by PatentIndex Score
16 records- 0198US8826213B1Parasitic capacitance extraction for FinFETsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 2, 2014·440 cites·20 claims
- 0297US8887106B2Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication processHO CHIA-MING·Filed 2012·Granted Nov 11, 2014·414 cites·20 claims
- 0394US7818698B2Accurate parasitic capacitance extraction for ultra large scale integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Oct 19, 2010·15 cites·8 claims
- 0493US8887116B2Flexible pattern-oriented 3D profile for advanced process nodesTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Nov 11, 2014·46 cites·22 claims
- 0590US8572537B2Accurate parasitic capacitance extraction for ultra large scale integrated circuitsSU KE-YING·Filed 2012·Granted Oct 29, 2013·7 cites·20 claims
- 0685US8904314B1RC extraction for multiple patterning layout designTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 2, 2014·8 cites·20 claims
- 0784US8214784B2Accurate parasitic capacitance extraction for ultra large scale integrated circuitsSU KE-YING·Filed 2010·Granted Jul 3, 2012·4 cites·20 claims
- 0873US8954900B1Multi-patterning mask decomposition method and systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Feb 10, 2015·3 cites·20 claims
- 0971US9710588B2Method of generating modified layout for RC extractionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Jul 18, 2017·2 cites·20 claims
- 1070US6845582B1Photo-frame style photo albumFiled 2003·Granted Jan 25, 2005·22 cites·6 claims
- 1168US7181664B2Method on scan chain reordering for lowering VLSI power consumptionUNIV CHANG GUNG·Filed 2004·Granted Feb 20, 2007·14 cites·6 claims
- 1259US10140407B2Method, device and computer program product for integrated circuit layout generationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Nov 27, 2018·1 cites·20 claims
- 1357US9230052B2Method of generating a simulation model of a predefined fabrication processTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Jan 5, 2016·0 cites·20 claims
- 1456US10019548B2Method of generating modified layout and system thereforTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jul 10, 2018·0 cites·20 claims
- 1550US9218448B2Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layoutTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Dec 22, 2015·0 cites·20 claims
- 1648US9922162B2Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Mar 20, 2018·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →