Inventor · disambiguated record
Chin-Hsiung Ho
Also filed as: HO CHIN-HSIUNG
11 granted patents·476 citations·filing 1996–2002
92Inventor score
Files withTAIWAN SEMICONDUCTOR MFG11
Top patents by PatentIndex Score
11 records- 0188US6020255ADual damascene interconnect process with borderless contactTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Feb 1, 2000·105 cites·32 claims
- 0287US6037204ASilicon and arsenic double implanted pre-amorphization process for salicide technologyTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Mar 14, 2000·94 cites·26 claims
- 0384US5674775AIsolation trench with a rounded top edge using an etch buffer layerTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Oct 7, 1997·79 cites·14 claims
- 0483US6555477B1Method for preventing Cu CMP corrosionTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Apr 29, 2003·33 cites·20 claims
- 0578US6083824ABorderless contactTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jul 4, 2000·56 cites·36 claims
- 0678US6063695ASimplified process for the fabrication of deep clear laser marks using a photoresist maskTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted May 16, 2000·57 cites·15 claims
- 0755US6716740B2Method for depositing silicon oxide incorporating an outgassing stepTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Apr 6, 2004·6 cites·20 claims
- 0854US5821153AMethod to reduce field oxide loss from etchesTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted Oct 13, 1998·20 cites·16 claims
- 0953US6207538B1Method for forming n and p wells in a semiconductor substrate using a single masking stepTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Mar 27, 2001·14 cites·17 claims
- 1044US6103581AMethod for producing shallow trench isolation structureTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Aug 15, 2000·12 cites·15 claims
- 1130US6647998B2Electrostatic charge-free solvent-type dryer for semiconductor wafersTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Nov 18, 2003·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →