Inventor · disambiguated record
Chih-Tsun Huang
Also filed as: HUANG CHIH-TSUN
11 granted patents·7 pending applications·190 citations·filing 1999–2024
89Inventor score
Top patents by PatentIndex Score
18 records- 0188US6934900B1Test pattern generator for SRAM and DRAMGLOBAL UNICHIP CORP·Filed 2001·Granted Aug 23, 2005·62 cites·68 claims
- 0288US6415403B1Programmable built in self test for embedded DRAMGLOBAL UNICHIP CORP·Filed 1999·Granted Jul 2, 2002·83 cites·23 claims
- 0383US7904768B2Probing system for integrated circuit devicesNAT UNIV TSING HUA·Filed 2008·Granted Mar 8, 2011·11 cites·21 claims
- 0473US7675309B2Probing system for integrated circuit deviceUNIV TSINGHUA·Filed 2009·Granted Mar 9, 2010·7 cites·17 claims
- 0567US7065689B2Diagonal testing method for flash memoriesUNIV TSING HUA·Filed 2003·Granted Jun 20, 2006·19 cites·20 claims
- 0665US11657273B2Hardware structure aware adaptive learning based power modeling method and systemIND TECH RES INST·Filed 2019·Granted May 23, 2023·1 cites·20 claims
- 0763US10365829B2Memory transaction-level modeling method and systemIND TECH RES INST·Filed 2016·Granted Jul 30, 2019·1 cites·30 claims
- 0863US2025209135A1Algorithms for sparse attention operationsIND TECH RES INST·Filed 2024·Application pending·0 cites
- 0962US7861070B2Trace compression method for debug and trace interface wherein differences of register contents between logically adjacent registers are packed and increases of program counter addresses are categorizedNAT UNIV TSING HUA·Filed 2008·Granted Dec 28, 2010·3 cites·12 claims
- 1053US2024152731A1Hardware-aware zero-cost neural network architecture search system and network potential evaluation method thereofIND TECH RES INST·Filed 2023·Application pending·0 cites
- 1150US11551066B2Deep neural networks (DNN) hardware accelerator and operation method thereofIND TECH RES INST·Filed 2019·Granted Jan 10, 2023·0 cites·24 claims
- 1248US12190224B2Processing elements array that includes delay queues between processing elements to hold shared dataIND TECH RES INST·Filed 2020·Granted Jan 7, 2025·0 cites·3 claims
- 1347US2010172492A1Method for scheduling elliptic curve cryptography computationNAT UNIV TSING HUA·Filed 2009·Application pending·0 cites
- 1444US2006252375A1Probing system for integrated circuit devicesUNIV TSINGHUA·Filed 2005·Application pending·0 cites
- 1542US2007232240A1Probing system for integrated circuit devicesUNIV TSINGHUA·Filed 2007·Application pending·0 cites
- 1636US7117409B2Multi-port memory testing method utilizing a sequence folding scheme for testing time reductionUNIV TSINGHUA·Filed 2003·Granted Oct 3, 2006·3 cites·8 claims
- 1735US2017169150A1Method for system simulation and non-transitory computer-readable recording medium thereofIND TECH RES INST·Filed 2015·Application pending·0 cites
- 1826US2004233767A1Method and system of fault patterns oriented defect diagnosis for memoriesFiled 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →