Inventor · disambiguated record
Chiao-Ti Huang
Also filed as: HUANG CHIAO-TI
2 granted patents·42 pending applications·0 citations·filing 2019–2025
25Inventor score
Top patents by PatentIndex Score
44 records- 0171US2025324690A1Nanoribbon-based transistors with etch stop layer to assist subfin removalINTEL CORP·Filed 2025·Application pending·0 cites
- 0270US2025323127A1Integrated circuit structure with deep via bar width tuningINTEL CORP·Filed 2025·Application pending·0 cites
- 0366US12289924B2Transistors having increased effective channel widthOMNIVISION TECH INC·Filed 2023·Granted Apr 29, 2025·0 cites·15 claims
- 0465US2025112120A1Integrated circuit structure with deep via bar width tuningINTEL CORP·Filed 2023·Application pending·0 cites
- 0560US2024290835A1Nanoribbon-based transistors with etch stop layer to assist subfin removalINTEL CORP·Filed 2023·Application pending·0 cites
- 0655US2025194211A1Conductive via with front-side and back-side connections with a source or drain regionINTEL CORP·Filed 2023·Application pending·0 cites
- 0755US2025220990A1Gate cut plug with thin hermetic liner and low-k fill for reduced capacitance and oxidationINTEL CORP·Filed 2023·Application pending·0 cites
- 0855US2025142948A1Integrated circuit devices with self-aligned via-to-jumper connectionsINTEL CORP·Filed 2023·Application pending·0 cites
- 0954US2025212463A1Metal-all-around contact structure coupled with a source or drain regionINTEL CORP·Filed 2023·Application pending·0 cites
- 1054US2025204000A1Integrated circuit device with co-metalized electrical contactINTEL CORP·Filed 2023·Application pending·0 cites
- 1154US2025107212A1Airgap spacer between gate electrode and source or drain contactINTEL CORP·Filed 2023·Application pending·0 cites
- 1254US2025176255A1Back-side nanoribbon removalINTEL CORP·Filed 2023·Application pending·0 cites
- 1354US2025212470A1Integrated circuit device with backside isolaton regionINTEL CORP·Filed 2023·Application pending·0 cites
- 1454US2025204035A1Integrated circuit device with dielectric cut at n-p boundaryINTEL CORP·Filed 2023·Application pending·0 cites
- 1554US2025098260A1Integrated circuit structures with patch spacersINTEL CORP·Filed 2023·Application pending·0 cites
- 1654US2025113559A1Trench contact structure with etch-stop layerINTEL CORP·Filed 2023·Application pending·0 cites
- 1754US2025096114A1Via structure with improved substrate groundingINTEL CORP·Filed 2023·Application pending·0 cites
- 1854US2025089310A1Through-gate structure with an airgap spacer in a semiconductor deviceINTEL CORP·Filed 2023·Application pending·0 cites
- 1953US2025194179A1Integrated circuit structures with backside contacts and asymmetric source and drain regionsCHU TAO·Filed 2023·Application pending·0 cites
- 2053US2025113547A1Integrated circuit structures with internal spacers for 2d channel materialsINTEL CORP·Filed 2023·Application pending·0 cites
- 2153US2025169130A1Integrated circuit structures with different nanoribbon thicknessesINTEL CORP·Filed 2023·Application pending·0 cites
- 2253US2025087530A1Lateral etching process to remove metal gate foot structuresINTEL CORP·Filed 2023·Application pending·0 cites
- 2353US2025140649A1Integrated circuit devices with backside semiconductor structuresINTEL CORP·Filed 2023·Application pending·0 cites
- 2452US2025113595A1Multiple voltage threshold integrated circuit structure with local layout effect tuningINTEL CORP·Filed 2023·Application pending·0 cites
- 2552US2025107156A1Dielectric isolation between epitaxial regions and subfin regionsINTEL CORP·Filed 2023·Application pending·0 cites
- 2652US2025107175A1Integrated circuit structures having reduced local layout effectsINTEL CORP·Filed 2023·Application pending·0 cites
- 2751US2025194070A1Integrated circuit structures with transistor gate-channel arrangements for static random-access memoryCHU TAO·Filed 2023·Application pending·0 cites
- 2851US2025113600A1Metal gate cut with reduced oxidation and parasitic capacitanceINTEL CORP·Filed 2023·Application pending·0 cites
- 2951US2024304621A1Fabrication of nanoribbon-based transistors using patterned foundationINTEL CORP·Filed 2023·Application pending·0 cites
- 3051US2024290788A1Metal gate fabrication for nanoribbon-based transistorsINTEL CORP·Filed 2023·Application pending·0 cites
- 3150US2025006734A1Performance optimization of transistors sharing channel structures of varying widthINTEL CORP·Filed 2023·Application pending·0 cites
- 3250US2024321987A1Long channel fin transistors in nanoribbon-based devicesINTEL CORP·Filed 2023·Application pending·0 cites
- 3350US2025159932A1Integrated circuit structures having metal gate cut plug structuresINTEL CORP·Filed 2023·Application pending·0 cites
- 3450US2024178273A1Integrated circuit structures with source or drain contacts having enhanced contact areaINTEL CORP·Filed 2022·Application pending·0 cites
- 3550US2024321887A1Integrated circuit device with reduced n-p boundary effectINTEL CORP·Filed 2023·Application pending·0 cites
- 3650US2025203975A1Integrated circuit device with semiconductor structure extending across gate in isolaton regionXU GUOWEI·Filed 2023·Application pending·0 cites
- 3750US2024321859A1Integrated circuit device with performance-enhancing layoutINTEL CORP·Filed 2023·Application pending·0 cites
- 3849US2025006733A1Integrated circuit structures with differential epitaxial source or drain dentINTEL CORP·Filed 2023·Application pending·0 cites
- 3949US2024213100A1Metal gate cut with hybrid material fillINTEL CORP·Filed 2022·Application pending·0 cites
- 4049US2024332088A1Modulation of chip performance by controlling transistor gate profileINTEL CORP·Filed 2023·Application pending·0 cites
- 4149US2024334669A1Buried low-k dielectric to protect source/drain to gate connectionINTEL CORP·Filed 2023·Application pending·0 cites
- 4248US2024178101A1Integrated circuit structure with recessed trench contact and deep boundary viaINTEL CORP·Filed 2022·Application pending·0 cites
- 4348US2024304619A1Integrated circuit device with backside fin trim isolationXU GUOWEI·Filed 2023·Application pending·0 cites
- 4443US11121169B2Metal vertical transfer gate with high-k dielectric passivation liningOMNIVISION TECH INC·Filed 2019·Granted Sep 14, 2021·0 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →