Inventor · disambiguated record
Chung-Shan Kuo
Also filed as: KUO CHUNG-SHAN
15 granted patents·77 citations·filing 2005–2021
91Inventor score
Files withELITE SEMICONDUCTOR ESMT6CONVERSANT INTELLECTUAL PROPERTY MAN INC3KUO CHUNG SHAN3CHEN CHUNG ZEN2MOSAID TECH INCORPORATED1
Top patents by PatentIndex Score
15 records- 0185US7542352B1Bit line precharge circuitELITE SEMICONDUCTOR ESMT·Filed 2008·Granted Jun 2, 2009·18 cites·12 claims
- 0284US7443230B2Charge pump circuitELITE SEMICONDUCTOR ESMT·Filed 2006·Granted Oct 28, 2008·22 cites·7 claims
- 0376US9298557B2Method of booting system having non-volatile memory device with erase checking and calibration mechanism and related memory deviceELITE SEMICONDUCTOR ESMT·Filed 2013·Granted Mar 29, 2016·5 cites·17 claims
- 0474US8456922B2Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltageCHEN CHUNG-ZEN·Filed 2012·Granted Jun 4, 2013·3 cites·20 claims
- 0574US8189396B2Word line driver in a hierarchical NOR flash memoryCHEN CHUNG-ZEN·Filed 2006·Granted May 29, 2012·6 cites·17 claims
- 0668US11594281B2Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltageMOSAID TECH INCORPORATED·Filed 2021·Granted Feb 28, 2023·0 cites·20 claims
- 0767US8848476B2Flash memory device and associated charge pump circuitKUO CHUNG SHAN·Filed 2011·Granted Sep 30, 2014·4 cites·10 claims
- 0865US7277329B2Erase method to reduce erase time and to prevent over-eraseELITE SEMICONDUCTOR ESMT·Filed 2005·Granted Oct 2, 2007·6 cites·10 claims
- 0964US7924610B2Method for conducting over-erase correctionELITE SEMICONDUCTOR ESMT·Filed 2009·Granted Apr 12, 2011·7 cites·6 claims
- 1062US10468109B2Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltageCONVERSANT INTELLECTUAL PROPERTY MAN INC·Filed 2015·Granted Nov 5, 2019·1 cites·20 claims
- 1159US9214233B2Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltageCONVERSANT INTELLECTUAL PROPERTY MAN INC·Filed 2013·Granted Dec 15, 2015·1 cites·20 claims
- 1255US10923194B2Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltageCONVERSANT INTELLECTUAL PROPERTY MAN INC·Filed 2019·Granted Feb 16, 2021·0 cites·15 claims
- 1354US9378822B2Method for programming selected memory cells in nonvolatile memory device and nonvolatile memory device thereofELITE SEMICONDUCTOR ESMT·Filed 2014·Granted Jun 28, 2016·1 cites·16 claims
- 1454US8391069B2Programming method for nonvolatile semiconductor memory deviceKUO CHUNG SHAN·Filed 2011·Granted Mar 5, 2013·3 cites·8 claims
- 1532US8693266B2Apparatus and method for trimming reference cell in semiconductor memory deviceKUO CHUNG-SHAN·Filed 2011·Granted Apr 8, 2014·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →