Inventor · disambiguated record
Chung Woh Lai
Also filed as: LAI CHUNG WOH
24 granted patents·6 pending applications·142 citations·filing 2000–2014
95Inventor score
Top patents by PatentIndex Score
30 records- 0193US7838372B2Methods of manufacturing semiconductor devices and structures thereofINFINEON TECHNOLOGIES AG·Filed 2008·Granted Nov 23, 2010·25 cites·22 claims
- 0291US7445978B2Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOSCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Nov 4, 2008·22 cites·31 claims
- 0384US7977185B2Method and apparatus for post silicide spacer removalIBM·Filed 2005·Granted Jul 12, 2011·9 cites·14 claims
- 0484US7256084B2Composite stress spacerCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Aug 14, 2007·12 cites·19 claims
- 0581US7935593B2Stress optimization in dual embedded epitaxially grown semiconductor processingSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted May 3, 2011·7 cites·27 claims
- 0680US8198194B2Methods of forming p-channel field effect transistors having SiGe source/drain regionsYANG JONG HO·Filed 2010·Granted Jun 12, 2012·8 cites·11 claims
- 0771US8624329B2Spacer-less low-K dielectric processesLEE YONG MENG·Filed 2009·Granted Jan 7, 2014·5 cites·18 claims
- 0871US6653227B1Method of cobalt silicidation using an oxide-Titanium interlayerCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Nov 25, 2003·21 cites·21 claims
- 0969US8716081B2Capacitor top plate over source/drain to form a 1T memory deviceTEO LEE WEE·Filed 2007·Granted May 6, 2014·4 cites·29 claims
- 1069US8274115B2Hybrid orientation substrate with stress layerTEO LEE WEE·Filed 2008·Granted Sep 25, 2012·4 cites·16 claims
- 1169US8138066B2Dislocation engineering using a scanned laserLAI CHUNG WOH·Filed 2008·Granted Mar 20, 2012·3 cites·10 claims
- 1269US7999325B2Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOSGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Aug 16, 2011·3 cites·20 claims
- 1368US7615427B2Spacer-less low-k dielectric processesCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Nov 10, 2009·3 cites·20 claims
- 1466US8178417B2Method of forming shallow trench isolation structures for integrated circuitsMISHRA SHAILENDRA·Filed 2008·Granted May 15, 2012·4 cites·23 claims
- 1566US8053327B2Method of manufacture of an integrated circuit system with self-aligned isolation structuresGLOBALFOUNDRIES SG PTE LTD·Filed 2006·Granted Nov 8, 2011·3 cites·10 claims
- 1661US7955936B2Semiconductor fabrication process including an SiGe rework methodCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Jun 7, 2011·1 cites·19 claims
- 1758US6383922B1Thermal stability improvement of CoSi2 film by stuffing in titaniumCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 7, 2002·8 cites·21 claims
- 1857US8865571B2Dislocation engineering using a scanned laserIBM·Filed 2014·Granted Oct 21, 2014·0 cites·2 claims
- 1957US8865572B2Dislocation engineering using a scanned laserIBM·Filed 2014·Granted Oct 21, 2014·0 cites·1 claims
- 2050US7767577B2Nested and isolated transistors with reduced impedance differenceCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Aug 3, 2010·0 cites·18 claims
- 2148US7795680B2Integrated circuit system employing selective epitaxial growth technologyCHARTERED SEMICONDUCTOR MFG·Filed 2007·Granted Sep 14, 2010·0 cites·20 claims
- 2248US2012294322A1Dislocation Engineering Using a Scanned LaserLAI CHUNG WOH·Filed 2012·Application pending·0 cites
- 2347US7999300B2Memory cell structure and method for fabrication thereofGLOBALFOUNDRIES SG PTE LTD·Filed 2009·Granted Aug 16, 2011·0 cites·22 claims
- 2447US2010009527A1Integrated circuit system employing single mask layer technique for well formationCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 2545US2008315317A1Semiconductor system having complementary strained channelsCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 2643US2012138823A1Dislocation Engineering Using a Scanned LaserLAI CHUNG WOH·Filed 2012·Application pending·0 cites
- 2741US8143651B2Nested and isolated transistors with reduced impedance differenceWIDODO JOHNNY·Filed 2010·Granted Mar 27, 2012·0 cites·19 claims
- 2841US7932178B2Integrated circuit having a plurality of MOSFET devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2006·Granted Apr 26, 2011·0 cites·6 claims
- 2940US2009146181A1Integrated circuit system employing diffused source/drain extensionsCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 3038US2009050972A1Strained Semiconductor Device and Method of Making SameLINDSAY RICHARD·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →