Inventor · disambiguated record
Chao-Wen Lay
Also filed as: LAY CHAO-WEN
12 granted patents·9 pending applications·26 citations·filing 2003–2025
85Inventor score
Top patents by PatentIndex Score
21 records- 0187US9659886B2Method of fabricating semiconductor device having voids between top metal layers of metal interconnectsNANYA TECHNOLOGY CORP·Filed 2016·Granted May 23, 2017·7 cites·7 claims
- 0280US2025212382A1Semiconductor device including dielectric layer with uneven thicknessNANYA TECHNOLOGY CORP·Filed 2024·Application pending·0 cites
- 0379US2025308991A1Manufacturing method of semiconductor deviceNANYA TECHNOLOGY CORP·Filed 2025·Application pending·0 cites
- 0478US12354909B2Semiconductor device with porous spacer made of low-K material and manufacturing method thereofNANYA TECHNOLOGY CORP·Filed 2023·Granted Jul 8, 2025·0 cites·5 claims
- 0577US2025365999A1Memory device having a container-shaped electrodeNANYA TECHNOLOGY CORP·Filed 2025·Application pending·0 cites
- 0674US2025212487A1Semiconductor device including dielectric layer with uneven thicknessNANYA TECHNOLOGY CORP·Filed 2024·Application pending·0 cites
- 0773US2025212491A1Semiconductor device including dielectric layer with uneven thicknessNANYA TECHNOLOGY CORP·Filed 2023·Application pending·0 cites
- 0871US2025212383A1Method for manufacturing semiconductor device including dielectric layer with uneven thicknessNANYA TECHNOLOGY CORP·Filed 2025·Application pending·0 cites
- 0969US11804404B2Method of forming a semicondcutor device using carbon containing spacer for a bitlineNANYA TECHNOLOGY CORP·Filed 2021·Granted Oct 31, 2023·0 cites·14 claims
- 1069US8921977B2Capacitor array and method of fabricating the sameHUANG JEN JUI·Filed 2011·Granted Dec 30, 2014·4 cites·13 claims
- 1162US2025386487A1Memory device and manufacturing method thereofNANYA TECHNOLOGY CORP·Filed 2024·Application pending·0 cites
- 1261US11882690B2Semiconductor structure having tapered bit lineNANYA TECHNOLOGY CORP·Filed 2022·Granted Jan 23, 2024·0 cites·19 claims
- 1360US11895829B2Method of manufacturing semiconductor structure having tapered bit lineNANYA TECHNOLOGY CORP·Filed 2022·Granted Feb 6, 2024·0 cites·16 claims
- 1459US7078748B2Multi-layer gate stack structure comprising a metal layer for a FET device, and method for fabricating the sameNANYA TECHNOLOGY CORP·Filed 2004·Granted Jul 18, 2006·9 cites·15 claims
- 1557US11462548B1Semicondcutor device and manufacturing method thereofNANYA TECHNOLOGY CORP·Filed 2021·Granted Oct 4, 2022·0 cites·17 claims
- 1657US2025203843A1Memory device and manufacturing method thereofNANYA TECHNOLOGY CORP·Filed 2023·Application pending·0 cites
- 1756US6759300B2Method for fabricating floating gateNANYA TECHNOLOGY CORP·Filed 2003·Granted Jul 6, 2004·6 cites·18 claims
- 1848US9418949B2Semiconductor device having voids between top metal layers of metal interconnectsNANYA TECHNOLOGY CORP·Filed 2013·Granted Aug 16, 2016·0 cites·9 claims
- 1941US2009087978A1Interconnect manufacturing processNANYA TECHNOLOGY CORP·Filed 2007·Application pending·0 cites
- 2039US8658051B2Lithography resolution improving methodCHO KUO-YAO·Filed 2008·Granted Feb 25, 2014·0 cites·14 claims
- 2133US8222163B2Method of flattening a recess in a substrate and fabricating a semiconductor structureLAY CHAO-WEN·Filed 2010·Granted Jul 17, 2012·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →