Inventor · disambiguated record
Choonghyun Lee
Also filed as: LEE CHOONGHYUN
402 granted patents·15 pending applications·1,566 citations·filing 2015–2024
99Inventor score
Top patents by PatentIndex Score
417 records- 0199US11075273B1Nanosheet electrostatic discharge structureIBM·Filed 2020·Granted Jul 27, 2021·20 cites·20 claims
- 0299US10763177B1I/O device for gate-all-around transistorsIBM·Filed 2019·Granted Sep 1, 2020·40 cites·20 claims
- 0399US10700064B1Multi-threshold voltage gate-all-around field-effect transistor devices with common gatesIBM·Filed 2019·Granted Jun 30, 2020·89 cites·20 claims
- 0499US10490559B1Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensionsIBM·Filed 2018·Granted Nov 26, 2019·71 cites·16 claims
- 0599US10236217B1Stacked field-effect transistors (FETs) with shared and non-shared gatesIBM·Filed 2017·Granted Mar 19, 2019·50 cites·17 claims
- 0699US10229986B1Vertical transport field-effect transistor including dual layer top spacerIBM·Filed 2017·Granted Mar 12, 2019·35 cites·8 claims
- 0798US11521927B2Buried power rail for scaled vertical transport field effect transistorIBM·Filed 2020·Granted Dec 6, 2022·4 cites·20 claims
- 0898US11211462B2Using selectively formed cap layers to form self-aligned contacts to source/drain regionsIBM·Filed 2020·Granted Dec 28, 2021·5 cites·16 claims
- 0998US10825736B1Nanosheet with selective dipole diffusion into high-kIBM·Filed 2019·Granted Nov 3, 2020·44 cites·20 claims
- 1098US10734286B1Multiple dielectrics for gate-all-around transistorsIBM·Filed 2019·Granted Aug 4, 2020·32 cites·17 claims
- 1198US10559566B1Reduction of multi-threshold voltage patterning damage in nanosheet device structureIBM·Filed 2018·Granted Feb 11, 2020·30 cites·16 claims
- 1298US10553696B2Full air-gap spacers for gate-all-around nanosheet field effect transistorsIBM·Filed 2017·Granted Feb 4, 2020·21 cites·17 claims
- 1398US10535733B2Method of forming a nanosheet transistorIBM·Filed 2018·Granted Jan 14, 2020·32 cites·9 claims
- 1498US10522649B2Inverse T-shaped contact structures having air gap spacersIBM·Filed 2018·Granted Dec 31, 2019·23 cites·10 claims
- 1598US10381438B2Vertically stacked NFETS and PFETS with gate-all-around structureIBM·Filed 2017·Granted Aug 13, 2019·25 cites·11 claims
- 1698US10319846B1Multiple work function nanosheet field-effect transistors with differential interfacial layer thicknessIBM·Filed 2018·Granted Jun 11, 2019·28 cites·10 claims
- 1798US10297668B1Vertical transport fin field effect transistor with asymmetric channel profileIBM·Filed 2018·Granted May 21, 2019·18 cites·10 claims
- 1898US10002791B1Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETSIBM·Filed 2017·Granted Jun 19, 2018·20 cites·10 claims
- 1998US9960272B1Bottom contact resistance reduction on VFETIBM·Filed 2017·Granted May 1, 2018·27 cites·18 claims
- 2097US11271106B2Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contactsIBM·Filed 2020·Granted Mar 8, 2022·4 cites·20 claims
- 2197US10957778B2Formation of air gap spacers for reducing parasitic capacitanceIBM·Filed 2020·Granted Mar 23, 2021·4 cites·20 claims
- 2297US10832962B1Formation of an air gap spacer using sacrificial spacer layerIBM·Filed 2019·Granted Nov 10, 2020·17 cites·18 claims
- 2397US10504794B1Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistorIBM·Filed 2018·Granted Dec 10, 2019·13 cites·15 claims
- 2497US10497796B1Vertical transistor with reduced gate length variationIBM·Filed 2018·Granted Dec 3, 2019·16 cites·18 claims
- 2597US10332809B1Method and structure to introduce strain in stack nanosheet field effect transistorIBM·Filed 2018·Granted Jun 25, 2019·15 cites·20 claims
- 2697US10319833B1Vertical transport field-effect transistor including air-gap top spacerIBM·Filed 2017·Granted Jun 11, 2019·15 cites·13 claims
- 2797US10283565B1Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive elementIBM·Filed 2017·Granted May 7, 2019·20 cites·14 claims
- 2897US10276687B1Formation of self-aligned bottom spacer for vertical transistorsIBM·Filed 2017·Granted Apr 30, 2019·15 cites·18 claims
- 2997US10115800B1Vertical fin bipolar junction transistor with high germanium content silicon germanium baseIBM·Filed 2017·Granted Oct 30, 2018·17 cites·12 claims
- 3097US9773875B1Fabrication of silicon-germanium fin structure having silicon-rich outer surfaceIBM·Filed 2016·Granted Sep 26, 2017·21 cites·13 claims
- 3197US9741822B1Simplified gate stack process to improve dual channel CMOS performanceIBM·Filed 2016·Granted Aug 22, 2017·14 cites·13 claims
- 3297US9595449B1Silicon-germanium semiconductor devices and method of makingIBM·Filed 2015·Granted Mar 14, 2017·22 cites·20 claims
- 3396US11784122B2Integrated circuit device and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2022·Granted Oct 10, 2023·5 cites·20 claims
- 3496US11362031B2Integrated circuit device and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2020·Granted Jun 14, 2022·6 cites·20 claims
- 3596US10916638B2Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistanceIBM·Filed 2018·Granted Feb 9, 2021·10 cites·14 claims
- 3696US10804165B2Source and drain isolation for CMOS nanosheet with one block maskIBM·Filed 2019·Granted Oct 13, 2020·12 cites·19 claims
- 3796US10553678B2Vertically stacked dual channel nanosheet devicesIBM·Filed 2017·Granted Feb 4, 2020·12 cites·10 claims
- 3896US10553679B2Formation of self-limited inner spacer for gate-all-around nanosheet FETIBM·Filed 2017·Granted Feb 4, 2020·14 cites·12 claims
- 3996US10553495B2Nanosheet transistors with different gate dielectrics and workfunction metalsIBM·Filed 2017·Granted Feb 4, 2020·9 cites·15 claims
- 4096US10546925B2Vertically stacked nFET and pFET with dual work functionIBM·Filed 2017·Granted Jan 28, 2020·10 cites·12 claims
- 4196US10483361B1Wrap-around-contact structure for top source/drain in vertical FETsIBM·Filed 2018·Granted Nov 19, 2019·11 cites·15 claims
- 4296US10475923B1Method and structure for forming vertical transistors with various gate lengthsIBM·Filed 2018·Granted Nov 12, 2019·11 cites·12 claims
- 4396US10446664B1Inner spacer formation and contact resistance reduction in nanosheet transistorsIBM·Filed 2018·Granted Oct 15, 2019·13 cites·18 claims
- 4496US10008417B1Vertical transport fin field effect transistors having different channel lengthsIBM·Filed 2017·Granted Jun 26, 2018·11 cites·15 claims
- 4595US10879352B2Vertically stacked nFETs and pFETs with gate-all-around structureIBM·Filed 2019·Granted Dec 29, 2020·9 cites·20 claims
- 4695US10748994B2Vertically stacked nFET and pFET with dual work functionIBM·Filed 2019·Granted Aug 18, 2020·7 cites·17 claims
- 4795US10734447B2Field-effect transistor unit cells for neural networks with differential weightsIBM·Filed 2018·Granted Aug 4, 2020·12 cites·19 claims
- 4895US10600885B2Vertical fin field effect transistor devices with self-aligned source and drain junctionsIBM·Filed 2018·Granted Mar 24, 2020·8 cites·14 claims
- 4995US10573723B1Vertical transport FETs with asymmetric channel profiles using dipole layersIBM·Filed 2018·Granted Feb 25, 2020·12 cites·11 claims
- 5095US10529716B1Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxyIBM·Filed 2018·Granted Jan 7, 2020·8 cites·17 claims
Showing the top 50 of 417 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →