Inventor · disambiguated record
Cheok-Kei Lei
Also filed as: LEI CHEOK-KEI
20 granted patents·4 pending applications·98 citations·filing 2011–2024
93Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD19TAIWAN SEMICONDUCTOR MFG2CHEN HSIAO-HUI1LEI CHEOK-KEI1LIN YI-TANG1
Top patents by PatentIndex Score
24 records- 0195US8875076B2System and methods for converting planar design to FinFET designTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Oct 28, 2014·35 cites·20 claims
- 0294US11030368B2Metal cut optimization for standard cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 8, 2021·3 cites·20 claims
- 0393US11392743B2MultiplexerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jul 19, 2022·3 cites·20 claims
- 0490US11694012B2MultiplexerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jul 4, 2023·1 cites·20 claims
- 0589US8726220B2System and methods for converting planar design to FinFET designLIN YI-TANG·Filed 2012·Granted May 13, 2014·21 cites·20 claims
- 0688US10691849B2Metal cut optimization for standard cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 23, 2020·4 cites·20 claims
- 0786US8978000B2Performance-driven and gradient-aware dummy insertion for gradient-sensitive arrayTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2012·Granted Mar 10, 2015·8 cites·20 claims
- 0884US11526649B2Capacitive isolation structure insert for reversed signalsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Dec 13, 2022·1 cites·20 claims
- 0984US8621406B2System and methods for converting planar design to FinFET designLEI CHEOK-KEI·Filed 2012·Granted Dec 31, 2013·13 cites·20 claims
- 1080US12106033B2Metal cut optimization for standard cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Oct 1, 2024·0 cites·20 claims
- 1179US10943050B2Capacitive isolation structure insert for reversed signalsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Mar 9, 2021·2 cites·20 claims
- 1279US2024362387A1Capacitive isolation structure insert for reversed signalsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1378US12147750B2MultiplexerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Nov 19, 2024·0 cites·20 claims
- 1478US11907633B2Layout for integrated circuit and the integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Feb 20, 2024·0 cites·20 claims
- 1578US2024411976A1MultiplexerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1677US12073162B2Capacitive isolation structure insert for reversed signalsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 27, 2024·0 cites·20 claims
- 1776US8789004B2Automatic flow of megacell generationCHEN HSIAO-HUI·Filed 2011·Granted Jul 22, 2014·7 cites·20 claims
- 1873US11734481B2Metal cut optimization for standard cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Aug 22, 2023·0 cites·20 claims
- 1967US11494543B2Layout for integrated circuit and the integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 8, 2022·0 cites·20 claims
- 2062US10685162B2Layout for integrated circuit and the integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 16, 2020·0 cites·20 claims
- 2157US10163883B2Layout method for integrated circuit and layout of the integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 25, 2018·0 cites·20 claims
- 2251US9659920B2Performance-driven and gradient-aware dummy insertion for gradient-sensitive arrayTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted May 23, 2017·0 cites·20 claims
- 2345US2021200927A1System and Method for Transistor Placement in Standard Cell LayoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Application pending·0 cites
- 2440US2013019219A1System and method for hierarchy reconstruction from flattened graphic database system layoutTAIWAN SEMICONDUCTOR MFG·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →