Inventor · disambiguated record
Chee How Lim
Also filed as: LIM CHEE H · LIM CHEE HOW
29 granted patents·1 pending application·971 citations·filing 1998–2021
97Inventor score
Top patents by PatentIndex Score
30 records- 0197US6157206AOn-chip terminationINTEL CORP·Filed 1998·Granted Dec 5, 2000·221 cites·20 claims
- 0295US6937075B2Method and apparatus for reducing lock time in dual charge-pump phase-locked loopsINTEL CORP·Filed 2003·Granted Aug 30, 2005·81 cites·19 claims
- 0393US6535047B2Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensationINTEL CORP·Filed 2001·Granted Mar 18, 2003·53 cites·26 claims
- 0491US6545522B2Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shiftingINTEL CORP·Filed 2001·Granted Apr 8, 2003·85 cites·15 claims
- 0591US6424170B1Apparatus and method for linear on-die termination in an open drain bus architecture systemINTEL CORP·Filed 2001·Granted Jul 23, 2002·97 cites·20 claims
- 0691US6411122B1Apparatus and method for dynamic on-die termination in an open-drain bus architecture systemINTEL CORP·Filed 2000·Granted Jun 25, 2002·101 cites·38 claims
- 0790US6748549B1Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clockINTEL CORP·Filed 2000·Granted Jun 8, 2004·48 cites·29 claims
- 0888US7100060B2Techniques for utilization of asymmetric secondary processing resourcesINTEL CORP·Filed 2002·Granted Aug 29, 2006·50 cites·46 claims
- 0988US6717455B2Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensationINTEL CORP·Filed 2003·Granted Apr 6, 2004·33 cites·16 claims
- 1087US6809606B2Voltage ID based frequency control for clock generating circuitINTEL CORP·Filed 2002·Granted Oct 26, 2004·33 cites·12 claims
- 1182US7695189B2System to calibrate on-die temperature sensorINTEL CORP·Filed 2008·Granted Apr 13, 2010·13 cites·5 claims
- 1274US6771134B2Frequency control for clock generating circuitINTEL CORP·Filed 2002·Granted Aug 3, 2004·19 cites·29 claims
- 1373US6509780B1Circuit compensation techniqueINTEL CORP·Filed 2001·Granted Jan 21, 2003·16 cites·17 claims
- 1471US6756810B2Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shiftingINTEL CORP·Filed 2003·Granted Jun 29, 2004·15 cites·9 claims
- 1568US6924710B2Voltage ID based frequency control for clock generating circuitINTEL CORP·Filed 2003·Granted Aug 2, 2005·13 cites·17 claims
- 1668US6522165B2Bus termination scheme for flexible uni-processor and dual processor platformsINTEL CORP·Filed 2001·Granted Feb 18, 2003·16 cites·20 claims
- 1767US6919769B2Method and apparatus for fast lock acquisition in self-biased phase locked loopsINTEL CORP·Filed 2003·Granted Jul 19, 2005·14 cites·20 claims
- 1863US7184503B2Multi-loop circuit capable of providing a delayed clock in phase locked loopsINTEL CORP·Filed 2005·Granted Feb 27, 2007·4 cites·3 claims
- 1963US6351136B1Passive voltage limiterINTEL CORP·Filed 1999·Granted Feb 26, 2002·17 cites·18 claims
- 2062US6842056B1Cascaded phase-locked loopsINTEL CORP·Filed 2003·Granted Jan 11, 2005·12 cites·15 claims
- 2159US6614317B2Variable lock window for a phase locked loopINTEL CORP·Filed 2001·Granted Sep 2, 2003·11 cites·32 claims
- 2257US12156331B2Technologies for power tunnels on circuit boardsINTEL CORP·Filed 2021·Granted Nov 26, 2024·0 cites·9 claims
- 2353US7417448B2System to calibrate on-die temperature sensorINTEL CORP·Filed 2006·Granted Aug 26, 2008·2 cites·12 claims
- 2452US7257756B2Digital frequency synthesis clocked circuitsINTEL CORP·Filed 2004·Granted Aug 14, 2007·8 cites·33 claims
- 2548US12396124B2Fan module interconnect apparatus for electronic devicesINTEL CORP·Filed 2020·Granted Aug 19, 2025·0 cites·14 claims
- 2648US11445608B2Chassis interconnect for an electronic deviceINTEL CORP·Filed 2020·Granted Sep 13, 2022·0 cites·21 claims
- 2744US7197659B2Global I/O timing adjustment using calibrated delay elementsINTEL CORP·Filed 2001·Granted Mar 27, 2007·4 cites·20 claims
- 2844US7023945B2Method and apparatus for jitter reduction in phase locked loopsINTEL CORP·Filed 2002·Granted Apr 4, 2006·3 cites·12 claims
- 2944US2006288244A1Techiniques for utilization of asymmetric secondary processing resourcesCAI ZHONG-NING·Filed 2006·Application pending·0 cites
- 3041US7199624B2Phase locked loop system capable of deskewingINTEL CORP·Filed 2003·Granted Apr 3, 2007·2 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →