Inventor · disambiguated record
Chooi Pei Lim
Also filed as: LIM CHOOI PEI
19 granted patents·87 citations·filing 2005–2022
92Inventor score
Top patents by PatentIndex Score
19 records- 0194US8793547B23D built-in self-test scheme for 3D assembly defect detectionALTERA CORP·Filed 2013·Granted Jul 29, 2014·33 cites·17 claims
- 0291US12026008B2Techniques for clock signal transmission in integrated circuits and interposersINTEL CORP·Filed 2022·Granted Jul 2, 2024·1 cites·19 claims
- 0383US9236864B1Stacked integrated circuit with redundancy in die-to-die interconnectsLOH SIANG POH·Filed 2012·Granted Jan 12, 2016·12 cites·5 claims
- 0480US7679397B1Techniques for precision biasing output driver for a calibrated on-chip termination circuitALTERA CORP·Filed 2005·Granted Mar 16, 2010·12 cites·29 claims
- 0578US11500412B2Techniques for clock signal transmission in integrated circuits and interposersINTEL CORP·Filed 2019·Granted Nov 15, 2022·2 cites·16 claims
- 0678US8758961B1Mask set for fabricating integrated circuits and method of fabricating integrated circuitsPLOFSKY JORDAN·Filed 2011·Granted Jun 24, 2014·5 cites·19 claims
- 0775US7404169B2Clock signal networks for structured ASIC devicesALTERA CORP·Filed 2005·Granted Jul 22, 2008·7 cites·14 claims
- 0874US9577649B1Methods and apparatus for reducing power in clock distribution networksALTERA CORP·Filed 2016·Granted Feb 21, 2017·5 cites·20 claims
- 0964US8786308B1Method and apparatus for providing signal routing controlALTERA CORP·Filed 2012·Granted Jul 22, 2014·2 cites·20 claims
- 1064US7622952B1Periphery clock signal distribution circuitry for structured ASIC devicesALTERA CORP·Filed 2008·Granted Nov 24, 2009·6 cites·20 claims
- 1160US8786080B2Systems including an I/O stack and methods for fabricating such systemsLIM CHOOI PEI·Filed 2011·Granted Jul 22, 2014·2 cites·14 claims
- 1254US9225335B2Clock signal networks for structured ASIC devicesALTERA CORP·Filed 2013·Granted Dec 29, 2015·0 cites·19 claims
- 1353US12316328B2Via configurable edge-combiner with duty cycle correctionINTEL CORP·Filed 2021·Granted May 27, 2025·0 cites·20 claims
- 1453US9401281B1Mask set for fabricating integrated circuits and method of fabricating integrated circuitsALTERA CORP·Filed 2014·Granted Jul 26, 2016·0 cites·20 claims
- 1552US9430433B1Multi-layer distributed networkALTERA CORP·Filed 2014·Granted Aug 30, 2016·0 cites·20 claims
- 1648US8595658B2Clock signal networks for structured ASIC devicesLIM CHOOI PEI·Filed 2008·Granted Nov 26, 2013·0 cites·24 claims
- 1745US10530367B2Clock synchronization in multi-die field programmable gate array devicesINTEL CORP·Filed 2018·Granted Jan 7, 2020·0 cites·22 claims
- 1845US8166429B1Multi-layer distributed networkOH KEONG HONG·Filed 2008·Granted Apr 24, 2012·0 cites·15 claims
- 1940US8683405B2Multi-layer distributed networkOH KEONG HONG·Filed 2012·Granted Mar 25, 2014·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →