Inventor · disambiguated record
Chunhui Mei
Also filed as: MEI CHUNHUI
14 granted patents·13 pending applications·47 citations·filing 2010–2024
89Inventor score
Top patents by PatentIndex Score
27 records- 0191US9652284B2GPU divergence barrierQUALCOMM INC·Filed 2013·Granted May 16, 2017·18 cites·28 claims
- 0290US10026145B2Resource sharing on shader processor of GPUQUALCOMM INC·Filed 2016·Granted Jul 17, 2018·10 cites·27 claims
- 0389US11977885B2Utilizing structured sparsity in systolic arraysINTEL CORP·Filed 2020·Granted May 7, 2024·2 cites·20 claims
- 0482US12189571B2Dual pipeline parallel systolic arrayINTEL CORP·Filed 2021·Granted Jan 7, 2025·1 cites·20 claims
- 0581US9569811B2Rendering graphics to overlapping binsQUALCOMM INC·Filed 2014·Granted Feb 14, 2017·6 cites·30 claims
- 0680US12405787B2Utilizing structured sparsity in systolic arraysINTEL CORP·Filed 2024·Granted Sep 2, 2025·0 cites·20 claims
- 0778US9679347B2Shader pipeline with shared data channelsQUALCOMM INC·Filed 2014·Granted Jun 13, 2017·5 cites·18 claims
- 0874US2025053613A1Random sparsity handling in a systolic arrayINTEL CORP·Filed 2024·Application pending·0 cites
- 0973US2025117359A1Dual pipeline parallel systolic arrayINTEL CORP·Filed 2024·Application pending·0 cites
- 1069US9123168B2Output ordering of domain coordinates for tessellationQUALCOMM INC·Filed 2013·Granted Sep 1, 2015·3 cites·26 claims
- 1165US11494163B2Conversion hardware mechanismINTEL CORP·Filed 2019·Granted Nov 8, 2022·1 cites·19 claims
- 1264US12086205B2Random sparsity handling in a systolic arrayINTEL CORP·Filed 2021·Granted Sep 10, 2024·0 cites·20 claims
- 1352US2024220420A1Locally biased cache replacement for clustered cache architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 1451US8577185B2Apparatus and method for interpolating and rendering image on mobile devicesMEI CHUNHUI·Filed 2010·Granted Nov 5, 2013·1 cites·16 claims
- 1551US2024220335A1Synchronization for data multicast in compute core clustersINTEL CORP·Filed 2022·Application pending·0 cites
- 1651US2025110741A1Supporting 8-bit floating point format for parallel computing and stochastic rounding operations in a graphics architectureINTEL CORP·Filed 2023·Application pending·0 cites
- 1751US2024220448A1Scalable and configurable clustered systolic arrayINTEL CORP·Filed 2022·Application pending·0 cites
- 1851US2024220254A1Data multicast in compute core clustersINTEL CORP·Filed 2022·Application pending·0 cites
- 1949US2024231957A9Named and cluster barriersINTEL CORP·Filed 2022·Application pending·0 cites
- 2049US2024111534A1Deterministic broadcasting from shared memoryINTEL CORP·Filed 2022·Application pending·0 cites
- 2149US2024112295A1Shared local registers for thread team processingINTEL CORP·Filed 2022·Application pending·0 cites
- 2249US2024111609A1Synchronization utilizing local team barriers for thread team processingINTEL CORP·Filed 2022·Application pending·0 cites
- 2348US2024160478A1Increasing processing resources in processing cores of a graphics environmentINTEL CORP·Filed 2022·Application pending·0 cites
- 2446US2023205587A1Thread group dispatch in a clustered graphics architectureINTEL CORP·Filed 2021·Application pending·0 cites
- 2540US10089708B2Constant multiplication with texture unit of graphics processing unitQUALCOMM INC·Filed 2016·Granted Oct 2, 2018·0 cites·27 claims
- 2639US10504462B2Non-linear processing of two-dimensional dataQUALCOMM INC·Filed 2018·Granted Dec 10, 2019·0 cites·25 claims
- 2738US9626762B2Stochastic rasterization using enhanced stencil operations on a graphics processing unit (GPU)QUALCOMM INC·Filed 2015·Granted Apr 18, 2017·0 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →