Inventor · disambiguated record
Charles R. Moore
Also filed as: MOORE CHARLES R · MOORE CHARLES R J · MOORE CHARLES ROBERT
18 granted patents·1 pending application·783 citations·filing 1967–2009
96Inventor score
Top patents by PatentIndex Score
19 records- 0196USD242945SLampMOORE CHARLES R·Filed 1975·Granted Jan 4, 1977·42 cites·1 claims
- 0294US6704860B1Data processing system and method for fetching instruction blocks in response to a detected block sequenceIBM·Filed 2000·Granted Mar 9, 2004·117 cites·23 claims
- 0392US7356692B2Method and system for enforcing access to a computing resource using a licensing attribute certificateSPYRUS INC·Filed 2005·Granted Apr 8, 2008·33 cites·48 claims
- 0491US4066964ACommunication systemROCKWELL INTERNATIONAL CORP·Filed 1967·Granted Jan 3, 1978·126 cites·54 claims
- 0589US6904523B2Method and system for enforcing access to a computing resource using a licensing attribute certificateSPYRUS INC·Filed 2002·Granted Jun 7, 2005·58 cites·47 claims
- 0689US6868491B1Processor and method of executing load instructions out-of-order having reduced hazard penaltyIBM·Filed 2000·Granted Mar 15, 2005·59 cites·18 claims
- 0786US5127091ASystem for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processorIBM·Filed 1989·Granted Jun 30, 1992·113 cites·32 claims
- 0885US6871273B1Processor and method of executing a load instruction that dynamically bifurcate a load instruction into separately executable prefetch and register operationsIBM·Filed 2000·Granted Mar 22, 2005·46 cites·14 claims
- 0982US6725358B1Processor and method having a load reorder queue that supports reservationsIBM·Filed 2000·Granted Apr 20, 2004·35 cites·18 claims
- 1080US6715062B1Processor and method for performing a hardware test during instruction execution in a normal modeIBM·Filed 2000·Granted Mar 30, 2004·30 cites·15 claims
- 1177US4075470AEmergency lampMOORE CHARLES R·Filed 1975·Granted Feb 21, 1978·35 cites·13 claims
- 1264US7096347B2Processor and method of testing a processor for hardware faults utilizing a pipeline interlocking test instructionMOORE CHARLES R·Filed 2001·Granted Aug 22, 2006·10 cites·19 claims
- 1363US6829702B1Branch target cache and method for efficiently obtaining target path instructions for tight program loopsIBM·Filed 2000·Granted Dec 7, 2004·9 cites·18 claims
- 1459US6816965B1Method and system for a policy enforcing moduleSPYRUS INC·Filed 1999·Granted Nov 9, 2004·40 cites·42 claims
- 1552US4916658ADynamic buffer controlIBM·Filed 1987·Granted Apr 10, 1990·21 cites·12 claims
- 1643US2009309382A1Slide-Out MechanismMOORE CHARLES R·Filed 2009·Application pending·0 cites
- 1737USD242944SDual lampMOORE CHARLES R·Filed 1975·Granted Jan 4, 1977·1 cites·1 claims
- 1837US3931730ARamp current apparatus and method of sensitivity testingUS ARMY·Filed 1974·Granted Jan 13, 1976·5 cites·6 claims
- 1936US4013941ATransformer voltage regulator responsive to input variationsMOORE CHARLES R·Filed 1976·Granted Mar 22, 1977·3 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →