Inventor · disambiguated record
Christopher P. Mozak
Also filed as: MOZAK CHRISTOPHER · MOZAK CHRISTOPHER P · MOZAK CHRISTOPHER PHILIP
72 granted patents·14 pending applications·870 citations·filing 2006–2025
99Inventor score
Top patents by PatentIndex Score
86 records- 0199US10210925B2Row hammer refresh commandINTEL CORP·Filed 2017·Granted Feb 19, 2019·75 cites·20 claims
- 0299US9865326B2Row hammer refresh commandINTEL CORP·Filed 2016·Granted Jan 9, 2018·83 cites·42 claims
- 0399US9747971B2Row hammer refresh commandINTEL CORP·Filed 2015·Granted Aug 29, 2017·84 cites·46 claims
- 0499US9236110B2Row hammer refresh commandBAINS KULJIT S·Filed 2012·Granted Jan 12, 2016·65 cites·30 claims
- 0598US9117544B2Row hammer refresh commandBAINS KULJIT·Filed 2013·Granted Aug 25, 2015·103 cites·15 claims
- 0697US9076499B2Refresh rate performance based on in-system weak bit detectionINTEL CORP·Filed 2012·Granted Jul 7, 2015·33 cites·23 claims
- 0796US8938573B2Row hammer condition monitoringGREENFIELD ZVIKA·Filed 2012·Granted Jan 20, 2015·88 cites·14 claims
- 0893US9934842B2Multiple rank high bandwidth memoryINTEL CORP·Filed 2016·Granted Apr 3, 2018·15 cites·16 claims
- 0992US7886174B2Memory link trainingINTEL CORP·Filed 2007·Granted Feb 8, 2011·31 cites·11 claims
- 1091US9218575B2Periodic training for unmatched signal receiverINTEL CORP·Filed 2013·Granted Dec 22, 2015·14 cites·20 claims
- 1190US12093195B2Techniques for command bus training to a memory deviceINTEL CORP·Filed 2023·Granted Sep 17, 2024·2 cites·20 claims
- 1290US11061590B2Efficiently training memory device chip select controlINTEL CORP·Filed 2019·Granted Jul 13, 2021·7 cites·19 claims
- 1390US10416912B2Efficiently training memory device chip select controlINTEL CORP·Filed 2017·Granted Sep 17, 2019·8 cites·18 claims
- 1490US9026725B2Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signalsINTEL CORP·Filed 2012·Granted May 5, 2015·20 cites·21 claims
- 1589US10446222B2Memory subsystem I/O performance based on in-system empirical testingINTEL CORP·Filed 2016·Granted Oct 15, 2019·5 cites·21 claims
- 1689US10031868B2Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal linesINTEL CORP·Filed 2017·Granted Jul 24, 2018·4 cites·20 claims
- 1789US9330734B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemINTEL CORP·Filed 2013·Granted May 3, 2016·9 cites·13 claims
- 1888US11037607B2Strong arm latch with wide common mode rangeINTEL CORP·Filed 2018·Granted Jun 15, 2021·10 cites·26 claims
- 1987US8819474B2Active training of memory command timingSCHOENBORN THEODORE Z·Filed 2009·Granted Aug 26, 2014·21 cites·22 claims
- 2086US9658642B2Timing control for unmatched signal receiverINTEL CORP·Filed 2013·Granted May 23, 2017·8 cites·20 claims
- 2186US9536626B2Memory subsystem I/O performance based on in-system empirical testingSCHOENBORN THEODORE Z·Filed 2013·Granted Jan 3, 2017·9 cites·23 claims
- 2286US9009531B2Memory subsystem data bus stress testingINTEL CORP·Filed 2012·Granted Apr 14, 2015·10 cites·27 claims
- 2386US8996934B2Transaction-level testing of memory I/O and memory deviceINTEL CORP·Filed 2012·Granted Mar 31, 2015·10 cites·28 claims
- 2486US8582374B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemMOZAK CHRISTOPHER·Filed 2009·Granted Nov 12, 2013·18 cites·19 claims
- 2585US8929157B2Power efficient, single-ended termination using on-die voltage supplyINTEL CORP·Filed 2012·Granted Jan 6, 2015·11 cites·24 claims
- 2684US10839887B2Applying chip select for memory device identification and power management controlINTEL CORP·Filed 2017·Granted Nov 17, 2020·3 cites·22 claims
- 2784US10347319B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemINTEL CORP·Filed 2016·Granted Jul 9, 2019·5 cites·19 claims
- 2884US9003246B2Functional memory array testing with a transaction-level test engineINTEL CORP·Filed 2012·Granted Apr 7, 2015·9 cites·30 claims
- 2983US10437746B2Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal linesINTEL CORP·Filed 2018·Granted Oct 8, 2019·2 cites·21 claims
- 3083US8331176B2Method and system for evaluating effects of signal phase difference on a memory systemMOZAK CHRISTOPHER P·Filed 2009·Granted Dec 11, 2012·16 cites·19 claims
- 3182US9665527B2Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal linesINTEL CORP·Filed 2014·Granted May 30, 2017·4 cites·22 claims
- 3281US9009540B2Memory subsystem command bus stress testingMOZAK CHRISTOPHER P·Filed 2012·Granted Apr 14, 2015·8 cites·30 claims
- 3380US11675716B2Techniques for command bus training to a memory deviceINTEL CORP·Filed 2019·Granted Jun 13, 2023·3 cites·23 claims
- 3480US9792246B2Lower-power scrambling with improved signal integrityINTEL CORP·Filed 2014·Granted Oct 17, 2017·5 cites·28 claims
- 3580US8514533B2Method, apparatus, and system for protecting supply nodes from electrostatic dischargeMOZAK CHRISTOPHER P·Filed 2010·Granted Aug 20, 2013·6 cites·28 claims
- 3679US9373365B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemINTEL CORP·Filed 2014·Granted Jun 21, 2016·4 cites·17 claims
- 3778US2025272255A1Techniques for command bus training to a memory deviceINTEL CORP·Filed 2025·Application pending·0 cites
- 3877US12417195B2Techniques for command bus training to a memory deviceINTEL CORP·Filed 2024·Granted Sep 16, 2025·0 cites·20 claims
- 3977US10324490B2Timing control for unmatched signal receiverINTEL CORP·Filed 2017·Granted Jun 18, 2019·3 cites·30 claims
- 4077US7647476B2Common analog interface for multiple processor coresINTEL CORP·Filed 2006·Granted Jan 12, 2010·9 cites·16 claims
- 4176US10541018B2DDR memory bus with a reduced data strobe signal preamble timespanINTEL CORP·Filed 2017·Granted Jan 21, 2020·2 cites·20 claims
- 4276US9583176B1Variable weak leaker values during read operationsINTEL CORP·Filed 2015·Granted Feb 28, 2017·4 cites·20 claims
- 4375US9454329B2Mirroring memory commands to memory devicesCOX CHRISTOPHER E·Filed 2012·Granted Sep 27, 2016·4 cites·15 claims
- 4474US8248124B2Methods and apparatuses for delay-locked loops and phase-locked loopsMOSALIKANTI PRAVEEN·Filed 2010·Granted Aug 21, 2012·4 cites·23 claims
- 4574US7945050B2Suppressing power supply noise using data scrambling in double data rate memory systemsINTEL CORP·Filed 2007·Granted May 17, 2011·6 cites·21 claims
- 4672US9722663B2Interference testingINTEL CORP·Filed 2014·Granted Aug 1, 2017·3 cites·9 claims
- 4772US8868992B2Robust memory link testing using memory controllerSPRY BRYAN L·Filed 2009·Granted Oct 21, 2014·10 cites·13 claims
- 4869US12355445B2Techniques for duty cycle correctionINTEL CORP·Filed 2023·Granted Jul 8, 2025·0 cites·20 claims
- 4969US11675532B2Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data busSONY GROUP CORP·Filed 2021·Granted Jun 13, 2023·0 cites·20 claims
- 5069US10373948B2On-die system electrostatic discharge protectionINTEL CORP·Filed 2016·Granted Aug 6, 2019·2 cites·19 claims
Showing the top 50 of 86 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →