Inventor · disambiguated record
Chanaka D. Munasinghe
Also filed as: MUNASINGHE CHANAKA · MUNASINGHE CHANAKA D
14 granted patents·8 pending applications·18 citations·filing 2011–2023
87Inventor score
Top patents by PatentIndex Score
22 records- 0193US10056380B2Non-planar semiconductor device having doped sub-fin region and method to fabricate sameINTEL CORP·Filed 2013·Granted Aug 21, 2018·15 cites·11 claims
- 0289US10964697B2Non-planar semiconductor device having doped sub-fin region and method to fabricate sameINTEL CORP·Filed 2020·Granted Mar 30, 2021·2 cites·18 claims
- 0383US12191308B2Non-planar semiconductor device having doped sub-fin region and method to fabricate sameTAHOE RES LTD·Filed 2023·Granted Jan 7, 2025·0 cites·20 claims
- 0478US10622359B2Non-planar semiconductor device having doped sub-fin region and method to fabricate sameINTEL CORP·Filed 2019·Granted Apr 14, 2020·1 cites·20 claims
- 0574US11631673B2Non-planar semiconductor device having doped sub-fin region and method to fabricate sameTAHOE RES LTD·Filed 2021·Granted Apr 18, 2023·0 cites·20 claims
- 0669US10854607B2Isolation well doping with solid-state diffusion sources for finFET architecturesINTEL CORP·Filed 2020·Granted Dec 1, 2020·0 cites·20 claims
- 0764US10643999B2Doping with solid-state diffusion sources for finFET architecturesINTEL CORP·Filed 2019·Granted May 5, 2020·0 cites·15 claims
- 0863US10396079B2Non-planar semiconductor device having doped sub-fin region and method to fabricate sameINTEL CORP·Filed 2018·Granted Aug 27, 2019·0 cites·20 claims
- 0959US12471349B2Contact over active gate structures with uniform and conformal gate insulating cap layers for advanced integrated circuit structure fabricationINTEL CORP·Filed 2022·Granted Nov 11, 2025·0 cites·20 claims
- 1058US10340273B2Doping with solid-state diffusion sources for finFET architecturesINTEL CORP·Filed 2017·Granted Jul 2, 2019·0 cites·16 claims
- 1157US10090304B2Isolation well doping with solid-state diffusion sources for FinFET architecturesHAFEZ WALID M·Filed 2013·Granted Oct 2, 2018·0 cites·18 claims
- 1256US2025210510A1Integrated circuit structures with trench contact spacer structureINTEL CORP·Filed 2023·Application pending·0 cites
- 1354US12484281B2Topside plugs for epitaxial contact formationINTEL CORP·Filed 2022·Granted Nov 25, 2025·0 cites·20 claims
- 1451US2023207466A1Recessed and self-aligned buried power railGULER LEONARD P·Filed 2021·Application pending·0 cites
- 1550US12382721B2Integrated circuit structures having cut metal gates with dielectric spacer fillINTEL CORP·Filed 2021·Granted Aug 5, 2025·0 cites·18 claims
- 1650US2024429125A1Integrated circuit structure with deep via bar isolationINTEL CORP·Filed 2023·Application pending·0 cites
- 1750US2023187441A1Integrated circuit structures with trench contact flyover structureINTEL CORP·Filed 2021·Application pending·0 cites
- 1850US2023320057A1Recessed transistor terminal via jumpersINTEL CORP·Filed 2022·Application pending·0 cites
- 1949US2023317595A1Integrated circuit structures with pre-epitaxial deep via structureINTEL CORP·Filed 2022·Application pending·0 cites
- 2049US2024404917A1Self-aligned via patterning for backside interconnectsINTEL CORP·Filed 2023·Application pending·0 cites
- 2146US2023101725A1Silicon rich capping layer pre-amorphized with germanium and boron implants for thermal stability and low pmos contact resistivityINTEL CORP·Filed 2021·Application pending·0 cites
- 2243US9142421B2Double patterning lithography techniquesWALLACE CHARLES H·Filed 2011·Granted Sep 22, 2015·0 cites·25 claims
Join the waitlist — get patent alerts
Get an alert when Chanaka D. Munasinghe files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →