Inventor · disambiguated record
Chao-Hsien Peng
Also filed as: PENG CHAO-HSIEN
29 granted patents·5 pending applications·130 citations·filing 2003–2024
96Inventor score
Top patents by PatentIndex Score
34 records- 0196US9892933B2Lithography using multilayer spacer for reduced spacer footingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Feb 13, 2018·15 cites·20 claims
- 0294US8735280B1Method of semiconductor integrated circuit fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted May 27, 2014·13 cites·19 claims
- 0393US9728503B2Via pre-fill on back-end-of-the-line interconnect layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 8, 2017·9 cites·20 claims
- 0490US9159579B2Lithography using multilayer spacer for reduced spacer footingTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Oct 13, 2015·8 cites·19 claims
- 0590US9030013B2Interconnect structures comprising flexible buffer layersTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted May 12, 2015·9 cites·20 claims
- 0688US9252049B2Method for forming interconnect structure that avoids via recessTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Feb 2, 2016·7 cites·14 claims
- 0786US9466525B2Interconnect structures comprising flexible buffer layersTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Oct 11, 2016·4 cites·20 claims
- 0883US9646932B2Method for forming interconnect structure that avoids via recessTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 9, 2017·3 cites·20 claims
- 0981US9054161B2Method of semiconductor integrated circuit fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Jun 9, 2015·3 cites·20 claims
- 1080US9837310B2Method of manufacturing a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Dec 5, 2017·4 cites·20 claims
- 1179US8912041B2Method for forming recess-free interconnect structureTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 16, 2014·4 cites·20 claims
- 1278US9721887B2Method of forming metal interconnectionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 1, 2017·3 cites·18 claims
- 1376US7202162B2Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure and overlying materialsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Apr 10, 2007·18 cites·24 claims
- 1473US2024321632A1Semiconductor device including liner structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1571US9219033B2Via pre-fill on back-end-of-the-line interconnect layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Dec 22, 2015·2 cites·20 claims
- 1671US7405151B2Method for forming a semiconductor deviceTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Jul 29, 2008·3 cites·10 claims
- 1769US7078810B2Semiconductor device and fabrication method thereofTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jul 18, 2006·11 cites·9 claims
- 1865US10930552B2Method of semiconductor integrated circuit fabricationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Feb 23, 2021·0 cites·20 claims
- 1963US11908789B2Selective formation of conductor nanowiresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Feb 20, 2024·0 cites·20 claims
- 2063US8916469B2Method of fabricating copper damasceneTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 23, 2014·1 cites·19 claims
- 2160US12027419B2Semiconductor device including liner structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jul 2, 2024·0 cites·20 claims
- 2260US10453746B2Method of semiconductor integrated circuit fabricationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Oct 22, 2019·0 cites·20 claims
- 2360US7253501B2High performance metallization cap layerTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Aug 7, 2007·9 cites·13 claims
- 2459US9947583B2Method of semiconductor integrated circuit fabricationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Apr 17, 2018·0 cites·20 claims
- 2557US10490497B2Selective formation of conductor nanowiresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Nov 26, 2019·0 cites·20 claims
- 2656US9570347B2Method of semiconductor integrated circuit fabricationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Feb 14, 2017·0 cites·20 claims
- 2756US9385029B2Method for forming recess-free interconnect structureTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Jul 5, 2016·0 cites·20 claims
- 2853US8034709B2Method for forming composite barrier layerTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Oct 11, 2011·0 cites·13 claims
- 2950US7338903B2Sequential reducing plasma and inert plasma pre-treatment method for oxidizable conductor layerTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Mar 4, 2008·2 cites·50 claims
- 3046US7453149B2Composite barrier layerTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Nov 18, 2008·2 cites·15 claims
- 3142US2007152306A1Semiconductor device and fabrication method thereofTAIWAN SEMICONDUCTOR MFG·Filed 2006·Application pending·0 cites
- 3240US2005277292A1Method for fabricating low resistivity barrier for copper interconnectPENG CHAO-HSIEN·Filed 2004·Application pending·0 cites
- 3339US2005045092A1Method of multi-element compound deposition by atomic layer deposition for IC barrier layer applicationsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
- 3439US2005189075A1Pre-clean chamber with wafer heating apparatus and method of useTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Chao-Hsien Peng files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →