Inventor · disambiguated record
Chandrika Prasad
Also filed as: PRASAD CHANDRIKA
34 granted patents·3 pending applications·1,704 citations·filing 1981–2008
98Inventor score
Files withIBM37
Top patents by PatentIndex Score
37 records- 0199US6599778B2Chip and wafer integration process using vertical connectionsIBM·Filed 2001·Granted Jul 29, 2003·495 cites·16 claims
- 0295US6864165B1Method of fabricating integrated electronic chip with an interconnect deviceIBM·Filed 2003·Granted Mar 8, 2005·83 cites·16 claims
- 0395US6600224B1Thin film attachment to laminate using a dendritic interconnectionIBM·Filed 2000·Granted Jul 29, 2003·83 cites·19 claims
- 0494US7564118B2Chip and wafer integration process using vertical connectionsIBM·Filed 2008·Granted Jul 21, 2009·23 cites·18 claims
- 0594US6444560B1Process for making fine pitch connections between devices and structure made by the processIBM·Filed 2000·Granted Sep 3, 2002·65 cites·44 claims
- 0693US7388277B2Chip and wafer integration process using vertical connectionsIBM·Filed 2005·Granted Jun 17, 2008·20 cites·18 claims
- 0793US5436412AInterconnect structure having improved metallizationIBM·Filed 1993·Granted Jul 25, 1995·148 cites·30 claims
- 0891US6640021B2Fabrication of a hybrid integrated circuit device including an optoelectronic chipIBM·Filed 2001·Granted Oct 28, 2003·47 cites·20 claims
- 0990US6329609B1Method and structure to prevent distortion and expansion of organic spacer layer for thin film transfer-join technologyIBM·Filed 2000·Granted Dec 11, 2001·64 cites·15 claims
- 1088US6737297B2Process for making fine pitch connections between devices and structure made by the processIBM·Filed 2002·Granted May 18, 2004·32 cites·16 claims
- 1188US5757079AMethod for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages and the resulting MLTF structureIBM·Filed 1995·Granted May 26, 1998·90 cites·8 claims
- 1287US6856025B2Chip and wafer integration process using vertical connectionsIBM·Filed 2003·Granted Feb 15, 2005·35 cites·4 claims
- 1387US6281452B1Multi-level thin-film electronic packaging structure and related methodIBM·Filed 1998·Granted Aug 28, 2001·53 cites·21 claims
- 1484US6835589B2Three-dimensional integrated CMOS-MEMS device and process for making the sameIBM·Filed 2002·Granted Dec 28, 2004·48 cites·23 claims
- 1584US5534466AMethod of making area direct transfer multilayer thin film structureIBM·Filed 1995·Granted Jul 9, 1996·76 cites·19 claims
- 1683US7049697B2Process for making fine pitch connections between devices and structure made by the processIBM·Filed 2003·Granted May 23, 2006·22 cites·4 claims
- 1781US6090633AMultiple-plane pair thin-film structure and process of manufactureIBM·Filed 1999·Granted Jul 18, 2000·46 cites·15 claims
- 1880US6678949B2Process for forming a multi-level thin-film electronic packaging structureIBM·Filed 2001·Granted Jan 20, 2004·21 cites·8 claims
- 1979US6998327B2Thin film transfer join process and multilevel thin film moduleIBM·Filed 2002·Granted Feb 14, 2006·27 cites·12 claims
- 2075US4518112AProcess for controlled braze joining of electronic packaging elementsIBM·Filed 1982·Granted May 21, 1985·37 cites·3 claims
- 2174US6669833B2Process and apparatus for electroplating microscopic features uniformly across a large substrateIBM·Filed 2003·Granted Dec 30, 2003·20 cites·41 claims
- 2266US6099935AApparatus for providing solder interconnections to semiconductor and electronic packaging devicesIBM·Filed 1995·Granted Aug 8, 2000·24 cites·2 claims
- 2365US5747095AMethod for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packagesIBM·Filed 1997·Granted May 5, 1998·28 cites·10 claims
- 2462US6444919B1Thin film wiring scheme utilizing inter-chip site surface wiringIBM·Filed 1995·Granted Sep 3, 2002·29 cites·21 claims
- 2552US2007252287A1Integrated electronic chip and interconnect device and process for making the sameIBM·Filed 2007·Application pending·0 cites
- 2651US2006278998A1Integrated electronic chip and interconnect device and process for making the sameIBM·Filed 2006·Application pending·0 cites
- 2750US4634041AProcess for bonding current carrying elements to a substrate in an electronic system, and structures thereofIBM·Filed 1984·Granted Jan 6, 1987·10 cites·12 claims
- 2848US6724203B1Full wafer test configuration using memory metalsIBM·Filed 1997·Granted Apr 20, 2004·13 cites·22 claims
- 2947US6632314B1Method of making a lamination and surface planarization for multilayer thin film interconnectIBM·Filed 1999·Granted Oct 14, 2003·14 cites·11 claims
- 3047US5464682AMinimal capture pads applied to ceramic vias in ceramic substratesIBM·Filed 1993·Granted Nov 7, 1995·13 cites·15 claims
- 3143US4407860AProcess for producing an improved quality electrolessly deposited nickel layerIBM·Filed 1981·Granted Oct 4, 1983·11 cites·4 claims
- 3243US2005056943A1Integrated electronic chip and interconnect device and process for making the sameIBM·Filed 2004·Application pending·0 cites
- 3340US6323045B1Method and structure for top-to-bottom I/O nets repair in a thin film transfer and join processIBM·Filed 1999·Granted Nov 27, 2001·10 cites·16 claims
- 3440US6149048AApparatus and method for use in manufacturing semiconductor devicesIBM·Filed 1998·Granted Nov 21, 2000·7 cites·48 claims
- 3536US6448169B1Apparatus and method for use in manufacturing semiconductor devicesIBM·Filed 1995·Granted Sep 10, 2002·5 cites·7 claims
- 3635US5916451AMinimal capture pads applied to ceramic vias in ceramic substratesIBM·Filed 1995·Granted Jun 29, 1999·4 cites·16 claims
- 3727US4714982ASubstrate for a semiconductor package having improved I/O pin bondingIBM·Filed 1986·Granted Dec 22, 1987·1 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →