Inventor · disambiguated record
Chinsong Sul
Also filed as: SUL CHINSONG
18 granted patents·2 pending applications·229 citations·filing 2001–2020
94Inventor score
Top patents by PatentIndex Score
20 records- 0197US11144696B1Low cost design for test architectureSUL CHINSONG·Filed 2020·Granted Oct 12, 2021·10 cites·16 claims
- 0297US7698088B2Interface test circuitry and methodsSILICON IMAGE INC·Filed 2007·Granted Apr 13, 2010·66 cites·22 claims
- 0394US7840861B2Scan-based testing of devices implementing a test clock control structure (“TCCS”)SILICON IMAGE INC·Filed 2006·Granted Nov 23, 2010·34 cites·23 claims
- 0494US7793179B2Test clock control structures to generate configurable test clocks for scan-based testing of electronic circuits using programmable test clock controllersSILICON IMAGE INC·Filed 2006·Granted Sep 7, 2010·32 cites·34 claims
- 0588US7831877B2Circuitry to prevent peak power problems during scan shiftSILICON IMAGE INC·Filed 2007·Granted Nov 9, 2010·18 cites·16 claims
- 0685US8598898B2Testing of high-speed input-output devicesSUL CHINSONG·Filed 2010·Granted Dec 3, 2013·7 cites·29 claims
- 0784US8543873B2Multi-site testing of computer memory devices and serial IO portsSUL CHINSONG·Filed 2010·Granted Sep 24, 2013·9 cites·33 claims
- 0882US10338138B2Low cost design for test architectureSUL CHINSONG·Filed 2017·Granted Jul 2, 2019·3 cites·12 claims
- 0982US7984369B2Concurrent code checker and hardware efficient high-speed I/O having built-in self-test and debug featuresSILICON IMAGE INC·Filed 2007·Granted Jul 19, 2011·13 cites·56 claims
- 1081US8026726B2Fault testing for interconnectionsSILICON IMAGE INC·Filed 2009·Granted Sep 27, 2011·10 cites·38 claims
- 1180US8386867B2Computer memory test structureSILICON IMAGE INC·Filed 2009·Granted Feb 26, 2013·9 cites·29 claims
- 1277US8924805B2Computer memory test structureSILICON IMAGE INC·Filed 2013·Granted Dec 30, 2014·4 cites·37 claims
- 1373US8841974B2Test solution for ring oscillatorsSUL CHINSONG·Filed 2012·Granted Sep 23, 2014·4 cites·19 claims
- 1464US10712388B2Low cost design for test architectureSUL CHINSONG·Filed 2019·Granted Jul 14, 2020·0 cites·8 claims
- 1559US6751768B2Hierarchical creation of vectors for quiescent current (IDDQ) tests for system-on-chip circuitsAGILENT TECHNOLOGIES INC·Filed 2001·Granted Jun 15, 2004·10 cites·12 claims
- 1647US8667354B2Computer memory test structureSILICON IMAGE INC·Filed 2013·Granted Mar 4, 2014·0 cites·43 claims
- 1744US8839058B2Multi-site testing of computer memory devices and serial IO portsSILICON IMAGE INC·Filed 2013·Granted Sep 16, 2014·0 cites·11 claims
- 1843US9231567B2Test solution for a random number generatorSILICON IMAGE INC·Filed 2014·Granted Jan 5, 2016·0 cites·18 claims
- 1943US2004215437A1System and method for improved accuracy of standard cell timing modelsFiled 2003·Application pending·0 cites
- 2039US2012158346A1Iddq testing of cmos devicesSUL CHINSONG·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →