Inventor · disambiguated record
Chung-Hsing Wang
Also filed as: WANG CHUNG-HSING
202 granted patents·34 pending applications·848 citations·filing 2000–2025
99Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD173TAIWAN SEMICONDUCTOR MFG36WANG CHUNG-HSING5CHEN HUANG-YU3DYNACOLOR INC3
Top patents by PatentIndex Score
236 records- 0199US11282829B2Integrated circuit with mixed row heightsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Mar 22, 2022·16 cites·20 claims
- 0298US11727183B2Method of fabricating semiconductor device including standard-cell-adapted power grid arrangementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 15, 2023·3 cites·20 claims
- 0398US11715733B2Integrated circuit device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Aug 1, 2023·4 cites·20 claims
- 0498US11347922B2Method of fabricating semiconductor device including standard-cell-adapted power grid arrangementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted May 31, 2022·4 cites·20 claims
- 0597US11775725B2System and computer program product for integrated circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Oct 3, 2023·3 cites·20 claims
- 0697US11113443B1Integrated circuit with thicker metal lines on lower metallization layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 7, 2021·6 cites·20 claims
- 0797US11068637B1Systems and methods for context aware circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jul 20, 2021·9 cites·20 claims
- 0897US11068638B2Power grid, IC and method for placing power gridTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jul 20, 2021·4 cites·20 claims
- 0997US8826212B2Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formedTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 2, 2014·112 cites·20 claims
- 1097US8448100B1Tool and method for eliminating multi-patterning conflictsLIN HUNG LUNG·Filed 2012·Granted May 21, 2013·102 cites·18 claims
- 1195US8601409B1Compression method and system for use with multi-patterningCHEN HUANG-YU·Filed 2012·Granted Dec 3, 2013·30 cites·21 claims
- 1294US12191248B2Semiconductor arrangement and method of makingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jan 7, 2025·2 cites·20 claims
- 1394US11574108B2Block level design method for heterogeneous PG-structure cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 7, 2023·2 cites·20 claims
- 1494US11205032B2Integrated circuit design method, system and computer program productTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 21, 2021·6 cites·20 claims
- 1592US11669671B2Semiconductor device including PG-aligned cells and method of generating layout of sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 6, 2023·2 cites·20 claims
- 1692US10157258B2Method for evaluating failure-in-timeTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 18, 2018·6 cites·20 claims
- 1792US8990762B2Semiconductor device design method, system and computer program productTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Mar 24, 2015·19 cites·20 claims
- 1892US8813016B1Multiple via connections using connectivity ringsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Aug 19, 2014·15 cites·20 claims
- 1991US11251124B2Power grid structures and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Feb 15, 2022·6 cites·20 claims
- 2091US10050028B2Semiconductor device with reduced leakage currentTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Aug 14, 2018·8 cites·20 claims
- 2191US9852989B1Power grid of integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 26, 2017·8 cites·20 claims
- 2291US8694945B2Automatic place and route method for electromigration tolerant power distributionWANG CHUNG-HSING·Filed 2011·Granted Apr 8, 2014·13 cites·13 claims
- 2390US11769766B2Integrated circuit with mixed row heightsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Sep 26, 2023·1 cites·20 claims
- 2490US11669669B2Circuit layouts and related methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 6, 2023·2 cites·20 claims
- 2590US10943045B2Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Mar 9, 2021·4 cites·20 claims
- 2690US10878163B2Semiconductor device including PG-aligned cells and method of generating layout of sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 29, 2020·5 cites·20 claims
- 2790US10157840B2Integrated circuit having a high cell densityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 18, 2018·5 cites·20 claims
- 2890US9047433B2Cell and macro placement on fin gridTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jun 2, 2015·15 cites·20 claims
- 2990US8847284B2Integrated circuit with standard cellsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 30, 2014·12 cites·18 claims
- 3090US8252489B2Mask-shift-aware RC extraction for double patterning designSU KE-YING·Filed 2011·Granted Aug 28, 2012·7 cites·20 claims
- 3189US11532562B2Routing structure and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Dec 20, 2022·2 cites·20 claims
- 3289US9799639B2Power gating for three dimensional integrated circuits (3DIC)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Oct 24, 2017·4 cites·18 claims
- 3389US8307321B2Method for dummy metal and dummy via insertionLIU HUNG-YI·Filed 2010·Granted Nov 6, 2012·15 cites·18 claims
- 3488US10074641B2Power gating for three dimensional integrated circuits (3DIC)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Sep 11, 2018·3 cites·20 claims
- 3588US9477803B2Method of generating techfile having reduced corner variation valueTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Oct 25, 2016·9 cites·20 claims
- 3688US2025117564A1Method of fabricating semiconductor device including standard-cell-adapted power grid arrangementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 3788US2025322141A1Integrated circuit and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3887US8937358B2Channel doping extension beyond cell boundariesTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jan 20, 2015·8 cites·20 claims
- 3987US2025359341A1Backside conducting lines in integrated circuitsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4086US11593546B2Integrated circuit with thicker metal lines on lower metallization layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 28, 2023·1 cites·20 claims
- 4186US11055466B2Block level design method for heterogeneous PG-structure cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jul 6, 2021·2 cites·20 claims
- 4286US8359554B2Verification of 3D integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 2011·Granted Jan 22, 2013·10 cites·20 claims
- 4386US8060843B2Verification of 3D integrated circuitsWANG CHUNG-HSING·Filed 2008·Granted Nov 15, 2011·18 cites·20 claims
- 4486US2024387373A1Integrated Circuit Having a High Cell DensityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 4585US9287257B2Power gating for three dimensional integrated circuits (3DIC)TAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Mar 15, 2016·4 cites·20 claims
- 4684US12353816B2Structure and method of rectangular cell in semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jul 8, 2025·0 cites·20 claims
- 4784US12243821B2Conductive line structures and method of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Mar 4, 2025·0 cites·20 claims
- 4884US12182488B2Semiconductor device including standard-cell-adapted power grid arrangementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Dec 31, 2024·0 cites·20 claims
- 4984US11501052B1Conductor scheme selection and track planning for mixed-diagonal-Manhattan routingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 15, 2022·1 cites·20 claims
- 5084US10360337B2Method of forming conductive grid of integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jul 23, 2019·3 cites·20 claims
Showing the top 50 of 236 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →