Inventor · disambiguated record
Chen-Nan Yeh
Also filed as: YEH CHEN-NAN
45 granted patents·2 pending applications·1,594 citations·filing 2001–2019
98Inventor score
Files withTAIWAN SEMICONDUCTOR MFG24YU CHEN-HUA8TAIWAN SEMICONDUCTOR MFG CO LTD7CHANG CHENG-HUNG4HUNG SHIH-TING2
Top patents by PatentIndex Score
47 records- 0199US8048723B2Germanium FinFETs having dielectric punch-through stoppersTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Nov 1, 2011·265 cites·17 claims
- 0299US7667271B2Fin field-effect transistorsTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Feb 23, 2010·583 cites·18 claims
- 0398US8106459B2FinFETs having dielectric punch-through stoppersCHANG CHENG-HUNG·Filed 2008·Granted Jan 31, 2012·97 cites·9 claims
- 0497US8263462B2Dielectric punch-through stoppers for forming FinFETs having dual fin heightsHUNG SHIH-TING·Filed 2008·Granted Sep 11, 2012·68 cites·11 claims
- 0597US7560785B2Semiconductor device having multiple fin heightsTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Jul 14, 2009·59 cites·12 claims
- 0696US9299785B2Reducing resistance in source and drain regions of FinFETsTAIWAN SEMICONDUCTOR MFG·Filed 2015·Granted Mar 29, 2016·12 cites·20 claims
- 0796US8957477B2Germanium FinFETs having dielectric punch-through stoppersCHANG CHENG-HUNG·Filed 2011·Granted Feb 17, 2015·23 cites·17 claims
- 0896US8946828B2Semiconductor device having elevated structure and method of manufacturing the sameSUN SEY-PING·Filed 2010·Granted Feb 3, 2015·83 cites·15 claims
- 0996US7939889B2Reducing resistance in source and drain regions of FinFETsTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted May 10, 2011·36 cites·18 claims
- 1096US7902035B2Semiconductor device having multiple fin heightsTAIWAN SEMICONDUCTOR MFG·Filed 2009·Granted Mar 8, 2011·36 cites·13 claims
- 1196US7843000B2Semiconductor device having multiple fin heightsTAIWAN SEMICONDUCTOR MFG·Filed 2009·Granted Nov 30, 2010·39 cites·13 claims
- 1296US7612405B2Fabrication of FinFETs with multiple fin heightsTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Nov 3, 2009·55 cites·20 claims
- 1395US8912602B2FinFETs and methods for forming the sameHSU YU-RUNG·Filed 2010·Granted Dec 16, 2014·27 cites·20 claims
- 1495US8101994B2Semiconductor device having multiple fin heightsYU CHEN-HUA·Filed 2010·Granted Jan 24, 2012·19 cites·20 claims
- 1594US10312327B2FinFETs having dielectric punch-through stoppersTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jun 4, 2019·7 cites·20 claims
- 1694US9735042B2Dielectric punch-through stoppers for forming FinFETs having dual Fin heightsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 15, 2017·10 cites·20 claims
- 1793US9076689B2Reducing resistance in source and drain regions of FinFETsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jul 7, 2015·12 cites·20 claims
- 1893US7910994B2System and method for source/drain contact processingTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Mar 22, 2011·21 cites·20 claims
- 1992US9230959B2FinFETs having dielectric punch-through stoppersCHANG CHENG-HUNG·Filed 2011·Granted Jan 5, 2016·10 cites·19 claims
- 2091US9048259B2Dielectric punch-through stoppers for forming FinFETs having dual fin heightsHUNG SHIH-TING·Filed 2012·Granted Jun 2, 2015·11 cites·19 claims
- 2190US8617948B2Reducing resistance in source and drain regions of FinFETsYU CHEN-HUA·Filed 2011·Granted Dec 31, 2013·8 cites·15 claims
- 2289US7880303B2Stacked contact with low aspect ratioTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Feb 1, 2011·16 cites·19 claims
- 2386US9722025B2FinFETs having dielectric punch-through stoppersTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Aug 1, 2017·3 cites·19 claims
- 2486US7745890B2Hybrid metal fully silicided (FUSI) gateTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Jun 29, 2010·11 cites·20 claims
- 2584US10269616B2Method of fabricating semiconductor device isolation structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Apr 23, 2019·2 cites·20 claims
- 2684US8883597B2Method of fabrication of a FinFET elementCHANG CHENG-HUNG·Filed 2007·Granted Nov 11, 2014·13 cites·12 claims
- 2780US8143114B2System and method for source/drain contact processingYU CHEN-HUA·Filed 2011·Granted Mar 27, 2012·4 cites·20 claims
- 2877US6797630B1Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approachTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Sep 28, 2004·20 cites·34 claims
- 2976US7341943B2Post etch copper cleaning using dry plasmaTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Mar 11, 2008·6 cites·20 claims
- 3075US7629655B2Semiconductor device with multiple silicide regionsTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Dec 8, 2009·4 cites·20 claims
- 3171US8110890B2Method of fabricating semiconductor device isolation structureYU CHEN-HUA·Filed 2007·Granted Feb 7, 2012·2 cites·19 claims
- 3270US6616855B1Process to reduce surface roughness of low K damasceneTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Sep 9, 2003·13 cites·19 claims
- 3366US11133387B2FinFETs having dielectric punch-through stoppersTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Sep 28, 2021·0 cites·20 claims
- 3466US7029992B2Low oxygen content photoresist stripping process for low dielectric constant materialsTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Apr 18, 2006·9 cites·17 claims
- 3564US9601587B2Semiconductor device having elevated structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Mar 21, 2017·1 cites·20 claims
- 3657US9673082B2Method of fabricating semiconductor device isolation structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Jun 6, 2017·0 cites·20 claims
- 3755US9224606B2Method of fabricating semiconductor device isolation structureYU CHEN-HUA·Filed 2011·Granted Dec 29, 2015·0 cites·19 claims
- 3855US7169701B2Dual damascene trench formation to avoid low-K dielectric damageTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jan 30, 2007·6 cites·26 claims
- 3952US11038056B2System and method for source/drain contact processingYU CHEN HUA·Filed 2012·Granted Jun 15, 2021·0 cites·20 claims
- 4051US7538025B2Dual damascene process flow for porous low-k materialsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted May 26, 2009·3 cites·39 claims
- 4147US8450200B2Method for stacked contact with low aspect ratioYU CHEN-HUA·Filed 2010·Granted May 28, 2013·0 cites·20 claims
- 4247US7977772B2Hybrid metal fully silicided (FUSI) gateTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Jul 12, 2011·0 cites·20 claims
- 4344US7892909B2Polysilicon gate formation by in-situ dopingTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Feb 22, 2011·0 cites·20 claims
- 4444US7510940B2Method for fabricating dual-gate semiconductor deviceTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Mar 31, 2009·0 cites·14 claims
- 4541US2007004193A1Method for reworking low-k dual damascene photo resistTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 4641US2008194072A1Polysilicon gate formation by in-situ dopingYU CHEN-HUA·Filed 2007·Application pending·0 cites
- 4738US7094683B2Dual damascene method for ultra low K dielectricsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Aug 22, 2006·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →