Inventor · disambiguated record
Chenfeng Zhang
Also filed as: ZHANG CHENFENG
4 granted patents·1 pending application·57 citations·filing 2011–2022
76Inventor score
Technology areasG11C
Top patents by PatentIndex Score
5 records- 0192US8982637B1Vread bias allocation on word lines for read disturb reduction in 3D non-volatile memorySANDISK TECHNOLOGIES INC·Filed 2013·Granted Mar 17, 2015·23 cites·20 claims
- 0291US8885412B2Erase operation with controlled select gate voltage for 3D non-volatile memorySANDISK TECHNOLOGIES INC·Filed 2014·Granted Nov 11, 2014·18 cites·10 claims
- 0390US8908435B2Erase operation with controlled select gate voltage for 3D non-volatile memoryLI HAIBO·Filed 2011·Granted Dec 9, 2014·16 cites·28 claims
- 0454US11422886B2Die level data redundancy in solid state storage devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Aug 23, 2022·0 cites·12 claims
- 0554US2022308960A1Plane spanning data redundancy in solid state storage devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →