Inventor · disambiguated record
Conrado Blasco-Allue
Also filed as: BLASCO ALLUE CONRADO
13 granted patents·60 citations·filing 2012–2013
90Inventor score
Technology areasG06F
Top patents by PatentIndex Score
13 records- 0186US9367471B2Fetch width predictorBLASCO-ALLUE CONRADO·Filed 2012·Granted Jun 14, 2016·11 cites·17 claims
- 0285US9336003B2Multi-level dispatch for a superscalar processorAPPLE INC·Filed 2013·Granted May 10, 2016·10 cites·24 claims
- 0381US9311084B2RDA checkpoint optimizationAPPLE INC·Filed 2013·Granted Apr 12, 2016·6 cites·14 claims
- 0480US9575754B2Zero cycle moveKELLER JAMES B·Filed 2012·Granted Feb 21, 2017·7 cites·23 claims
- 0578US9405544B2Next fetch predictor return address stackAPPLE INC·Filed 2013·Granted Aug 2, 2016·5 cites·20 claims
- 0675US9317285B2Instruction set architecture mode dependent sub-size access of register with associated status indicationGUPTA SANDEEP·Filed 2012·Granted Apr 19, 2016·4 cites·19 claims
- 0773US9753733B2Methods, apparatus, and processors for packing multiple iterations of loop in a loop bufferBLASCO-ALLUE CONRADO·Filed 2012·Granted Sep 5, 2017·4 cites·18 claims
- 0873US9311100B2Usefulness indication for indirect branch prediction trainingAPPLE INC·Filed 2013·Granted Apr 12, 2016·3 cites·25 claims
- 0972US9557999B2Loop buffer learningBLASCO-ALLUE CONRADO·Filed 2012·Granted Jan 31, 2017·4 cites·19 claims
- 1068US9626185B2IT instruction pre-decodeAPPLE INC·Filed 2013·Granted Apr 18, 2017·2 cites·20 claims
- 1167US9311098B2Mechanism for reducing cache power consumption using cache way predictionAPPLE INC·Filed 2013·Granted Apr 12, 2016·2 cites·20 claims
- 1266US9430243B2Optimizing register initialization operationsKELLER JAMES B·Filed 2012·Granted Aug 30, 2016·2 cites·14 claims
- 1345US9672037B2Arithmetic branch fusionAPPLE INC·Filed 2013·Granted Jun 6, 2017·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →