Inventor · disambiguated record
Colin D. Yates
Also filed as: YATES COLIN · YATES COLIN D
10 granted patents·453 citations·filing 1997–2009
89Inventor score
Top patents by PatentIndex Score
10 records- 0197US6425117B1System and method for performing optical proximity correction on the interface between optical proximity corrected cellsLSI LOGIC CORP·Filed 1997·Granted Jul 23, 2002·393 cites·18 claims
- 0282US7541216B2Method of aligning deposited nanotubes onto an etched feature using a spacerNANTERO INC·Filed 2005·Granted Jun 2, 2009·11 cites·14 claims
- 0373US7313508B2Process window compliant corrections of design layoutLSI CORP·Filed 2002·Granted Dec 25, 2007·13 cites·25 claims
- 0469US6809824B1Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrateLSI LOGIC CORP·Filed 2001·Granted Oct 26, 2004·12 cites·19 claims
- 0564US7858979B2Method of aligning deposited nanotubes onto an etched feature using a spacerNANTERO INC·Filed 2009·Granted Dec 28, 2010·2 cites·12 claims
- 0663US7575693B2Method of aligning nanotubes and wires with an etched featureNANTERO INC·Filed 2005·Granted Aug 18, 2009·2 cites·16 claims
- 0754US8343373B2Method of aligning nanotubes and wires with an etched featureNANTERO INC·Filed 2009·Granted Jan 1, 2013·0 cites·20 claims
- 0850US5863825AAlignment mark contrast enhancementLSI LOGIC CORP·Filed 1997·Granted Jan 26, 1999·19 cites·19 claims
- 0946US6458508B1Method of protecting acid-catalyzed photoresist from chip-generated basic contaminantsLSI LOGIC CORP·Filed 2001·Granted Oct 1, 2002·1 cites·23 claims
- 1035US7016041B2Reticle overlay correctionLSI LOGIC CORP·Filed 2002·Granted Mar 21, 2006·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →