Inventor · disambiguated record
Daniel B. Aubertine
Also filed as: AUBERTINE DANIEL · AUBERTINE DANIEL B · AUBERTINE DANIEL BOUNE
20 granted patents·175 citations·filing 2007–2024
94Inventor score
Top patents by PatentIndex Score
20 records- 0198US8847281B2High mobility strained channels for fin-based transistorsCEA STEPHEN M·Filed 2012·Granted Sep 30, 2014·47 cites·22 claims
- 0297US9012284B2Nanowire transistor devices and forming techniquesGLASS GLENN A·Filed 2012·Granted Apr 21, 2015·37 cites·28 claims
- 0396US9064944B2Nanowire transistor with underlayer etch stopsKIM SEIYON·Filed 2013·Granted Jun 23, 2015·27 cites·14 claims
- 0493US9184294B2High mobility strained channels for fin-based transistorsINTEL CORP·Filed 2014·Granted Nov 10, 2015·11 cites·17 claims
- 0593US8957476B2Conversion of thin transistor elements from silicon to silicon germaniumGLASS GLENN A·Filed 2012·Granted Feb 17, 2015·16 cites·16 claims
- 0691US7663192B2CMOS device and method of manufacturing sameINTEL CORP·Filed 2008·Granted Feb 16, 2010·23 cites·20 claims
- 0789US9653584B2Pre-sculpting of Si fin elements prior to cladding for transistor channel applicationsINTEL CORP·Filed 2013·Granted May 16, 2017·7 cites·14 claims
- 0883US12294027B2Semiconductor device having doped epitaxial region and its methods of fabricationINTEL CORP·Filed 2024·Granted May 6, 2025·0 cites·13 claims
- 0979US9614060B2Nanowire transistor with underlayer etch stopsINTEL CORP·Filed 2016·Granted Apr 4, 2017·2 cites·12 claims
- 1074US8779477B2Enhanced dislocation stress transistorWEBER CORY·Filed 2008·Granted Jul 15, 2014·4 cites·10 claims
- 1161US10396203B2Pre-sculpting of Si fin elements prior to cladding for transistor channel applicationsINTEL CORP·Filed 2018·Granted Aug 27, 2019·0 cites·17 claims
- 1260US10084087B2Enhanced dislocation stress transistorINTEL CORP·Filed 2017·Granted Sep 25, 2018·0 cites·20 claims
- 1360US9231076B2Enhanced dislocation stress transistorINTEL CORP·Filed 2014·Granted Jan 5, 2016·0 cites·12 claims
- 1460US7833883B2Precursor gas mixture for depositing an epitaxial carbon-doped silicon filmINTEL CORP·Filed 2007·Granted Nov 16, 2010·1 cites·12 claims
- 1559US11171058B2Self-aligned 3-D epitaxial structures for MOS device fabricationINTEL CORP·Filed 2017·Granted Nov 9, 2021·0 cites·19 claims
- 1658US10014412B2Pre-sculpting of Si fin elements prior to cladding for transistor channel applicationsINTEL CORP·Filed 2017·Granted Jul 3, 2018·0 cites·20 claims
- 1758US9076814B2Enhanced dislocation stress transistorINTEL CORP·Filed 2014·Granted Jul 7, 2015·0 cites·16 claims
- 1857US9660078B2Enhanced dislocation stress transistorINTEL CORP·Filed 2015·Granted May 23, 2017·0 cites·13 claims
- 1954US9385221B2Nanowire transistor with underlayer etch stopsINTEL CORP·Filed 2015·Granted Jul 5, 2016·0 cites·7 claims
- 2047US10559689B2Crystallized silicon carbon replacement material for NMOS source/drain regionsINTEL CORP·Filed 2015·Granted Feb 11, 2020·0 cites·18 claims
Join the waitlist — get patent alerts
Get an alert when Daniel B. Aubertine files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →