Inventor · disambiguated record
David Cashman
Also filed as: CASHMAN DAVID
23 granted patents·1 pending application·176 citations·filing 2002–2022
95Inventor score
Top patents by PatentIndex Score
24 records- 0196US8860460B1Programmable integrated circuits with redundant circuitryALTERA CORP·Filed 2012·Granted Oct 14, 2014·23 cites·18 claims
- 0290US8427213B2Robust time borrowing pulse latchesLEWIS DAVID·Filed 2012·Granted Apr 23, 2013·8 cites·18 claims
- 0390US7583103B2Configurable time borrowing flip-flopsALTERA CORP·Filed 2007·Granted Sep 1, 2009·19 cites·12 claims
- 0490US6965249B2Programmable logic device with redundant circuitryALTERA CORP·Filed 2002·Granted Nov 15, 2005·39 cites·109 claims
- 0589US8115530B2Robust time borrowing pulse latchesLEWIS DAVID·Filed 2010·Granted Feb 14, 2012·7 cites·18 claims
- 0687US7558812B1Structures for LUT-based arithmetic in PLDsALTERA CORP·Filed 2003·Granted Jul 7, 2009·25 cites·12 claims
- 0785US7268584B1Adder circuitry for a programmable logic deviceALTERA CORP·Filed 2005·Granted Sep 11, 2007·15 cites·27 claims
- 0882US8222921B2Configurable time borrowing flip-flopsLEWIS DAVID·Filed 2011·Granted Jul 17, 2012·5 cites·23 claims
- 0981US7872512B2Robust time borrowing pulse latchesALTERA CORP·Filed 2008·Granted Jan 18, 2011·8 cites·7 claims
- 1079US7868655B2Configurable time borrowing flip-flopsALTERA CORP·Filed 2009·Granted Jan 11, 2011·7 cites·5 claims
- 1173US9658830B1Structures for LUT-based arithmetic in PLDsALTERA CORP·Filed 2014·Granted May 23, 2017·2 cites·23 claims
- 1272US8581624B2Integrated circuits with multi-stage logic regionsCASHMAN DAVID·Filed 2012·Granted Nov 12, 2013·4 cites·19 claims
- 1360US7456653B2Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocksALTERA CORP·Filed 2007·Granted Nov 25, 2008·3 cites·30 claims
- 1458US12332875B1Nested array batch processingDATABRICKS INC·Filed 2022·Granted Jun 17, 2025·0 cites·18 claims
- 1558US8788550B1Structures for LUT-based arithmetic in PLDsPADALIA KETAN·Filed 2009·Granted Jul 22, 2014·2 cites·20 claims
- 1658US2017322775A1Structures for lut-based arithmetic in pldsALTERA CORP·Filed 2017·Application pending·0 cites
- 1756US9030227B1Methods and apparatus for providing redundancy on multi-chip devicesALTERA CORP·Filed 2013·Granted May 12, 2015·1 cites·19 claims
- 1855US7724031B2Staggered logic array block architectureALTERA CORP·Filed 2007·Granted May 25, 2010·2 cites·15 claims
- 1954US7185306B1Method and apparatus for enhancing signal routabilityALTERA CORP·Filed 2004·Granted Feb 27, 2007·3 cites·23 claims
- 2051US7619443B1Programmable logic device architectures and methods for implementing logic in those architecturesALTERA CORP·Filed 2006·Granted Nov 17, 2009·1 cites·10 claims
- 2150US7508231B2Programmable logic device having redundancy with logic element granularityALTERA CORP·Filed 2007·Granted Mar 24, 2009·1 cites·18 claims
- 2246US7716623B1Programmable logic device architectures and methods for implementing logic in those architecturesALTERA CORP·Filed 2009·Granted May 11, 2010·0 cites·8 claims
- 2344US7579866B1Programmable logic device with configurable override of region-wide signalsALTERA CORP·Filed 2006·Granted Aug 25, 2009·1 cites·24 claims
- 2437US8242806B1Methods and systems for managing a write operationCASHMAN DAVID·Filed 2010·Granted Aug 14, 2012·0 cites·27 claims
Join the waitlist — get patent alerts
Get an alert when David Cashman files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →