Inventor · disambiguated record
Daniel J. Colglazier
Also filed as: COLGLAZIER DANIEL J · COLGLAZIER DANIEL JAMES
9 granted patents·4 pending applications·64 citations·filing 1997–2019
84Inventor score
Technology areasG06F
Top patents by PatentIndex Score
13 records- 0182US6715035B1Cache for processing data in a memory controller and a method of use thereof to reduce first transfer latencyIBM·Filed 2000·Granted Mar 30, 2004·37 cites·9 claims
- 0280US10387330B1Less recently and frequently used (LRAFU) cache replacement policyLENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD·Filed 2018·Granted Aug 20, 2019·3 cites·20 claims
- 0377US11030115B2Dataless cache entryLENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD·Filed 2019·Granted Jun 8, 2021·2 cites·20 claims
- 0459US8131943B2Structure for dynamic initial cache line coherency state assignment in multi-processor systemsCOLGLAZIER DANIEL J·Filed 2008·Granted Mar 6, 2012·3 cites·8 claims
- 0555US8745334B2Sectored cache replacement algorithm for reducing memory writebacksCOLGLAZIER DANIEL J·Filed 2009·Granted Jun 3, 2014·1 cites·15 claims
- 0651US2014208038A1Sectored cache replacement algorithm for reducing memory writebacksIBM·Filed 2014·Application pending·0 cites
- 0748US2014136785A1Enhanced cache coordination in a multilevel cacheIBM·Filed 2012·Application pending·0 cites
- 0848US2014136784A1Enhanced cache coordination in a multi-level cacheIBM·Filed 2012·Application pending·0 cites
- 0946US10176118B2Alternative direct-mapped cache and cache replacement methodLENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD·Filed 2016·Granted Jan 8, 2019·0 cites·20 claims
- 1043US5999721AMethod and system for the determination of performance characteristics of a cache design by simulating cache operations utilizing a cache output traceIBM·Filed 1997·Granted Dec 7, 1999·18 cites·25 claims
- 1142US10853267B2Adaptive method for selecting a cache line replacement algorithm in a direct-mapped cacheLENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD·Filed 2016·Granted Dec 1, 2020·0 cites·20 claims
- 1242US8838909B2Dynamic initial cache line coherency state assignment in multi-processor systemsCOLGLAZIER DANIEL J·Filed 2007·Granted Sep 16, 2014·0 cites·18 claims
- 1341US2008104323A1Method for identifying, tracking, and storing hot cache lines in an smp environmentCOLGLAZIER DANIEL J·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →