Inventor · disambiguated record
Daniel Gitlin
Also filed as: GITLIN DANIEL
18 granted patents·744 citations·filing 1997–2010
95Inventor score
Top patents by PatentIndex Score
18 records- 0197US6621325B2Structures and methods for selectively applying a well bias to portions of a programmable deviceXILINX INC·Filed 2001·Granted Sep 16, 2003·90 cites·21 claims
- 0297US5880620APass gate circuit with body bias controlXILINX INC·Filed 1997·Granted Mar 9, 1999·253 cites·22 claims
- 0395US6266269B1Three terminal non-volatile memory elementXILINX INC·Filed 2000·Granted Jul 24, 2001·113 cites·19 claims
- 0492US7294888B1CMOS-compatible non-volatile memory cell with lateral inter-poly programming layerXILINX INC·Filed 2005·Granted Nov 13, 2007·21 cites·14 claims
- 0591US7032194B1Layout correction algorithms for removing stress and other physical effect induced process deviationXILINX INC·Filed 2003·Granted Apr 18, 2006·87 cites·28 claims
- 0687US6268639B1Electrostatic-discharge protection circuitXILINX INC·Filed 1999·Granted Jul 31, 2001·64 cites·22 claims
- 0781US6549458B1Non-volatile memory array using gate breakdown structuresXILINX INC·Filed 2001·Granted Apr 15, 2003·25 cites·23 claims
- 0879US7936006B1Semiconductor device with backfilled isolationXILINX INC·Filed 2005·Granted May 3, 2011·8 cites·17 claims
- 0977US6645802B1Method of forming a zener diodeXILINX INC·Filed 2001·Granted Nov 11, 2003·20 cites·6 claims
- 1076US6522582B1Non-volatile memory array using gate breakdown structuresXILINX INC·Filed 2000·Granted Feb 18, 2003·20 cites·39 claims
- 1169US7687797B1Three-terminal non-volatile memory element with hybrid gate dielectricXILINX INC·Filed 2005·Granted Mar 30, 2010·3 cites·14 claims
- 1265US6740936B1Ballast resistor with reduced area for ESD protectionXILINX INC·Filed 2002·Granted May 25, 2004·12 cites·10 claims
- 1365US5870327AMixed mode RAM/ROM cell using antifusesXILINX INC·Filed 1997·Granted Feb 9, 1999·25 cites·5 claims
- 1464US7772093B2Method of and circuit for protecting a transistor formed on a dieXILINX INC·Filed 2007·Granted Aug 10, 2010·2 cites·15 claims
- 1552US7688639B1CMOS-compatible non-volatile memory cell with lateral inter-poly programming layerXILINX INC·Filed 2007·Granted Mar 30, 2010·0 cites·9 claims
- 1648US7956385B1Circuit for protecting a transistor during the manufacture of an integrated circuit deviceXILINX INC·Filed 2010·Granted Jun 7, 2011·0 cites·18 claims
- 1748US7839693B1Method of fabricating CMOS-compatible non-volatile memory cell with lateral inter-poly programming layerXILINX INC·Filed 2010·Granted Nov 23, 2010·0 cites·17 claims
- 1844US8436656B2Method and apparatus for saving power in an integrated circuitGITLIN DANIEL·Filed 2009·Granted May 7, 2013·1 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →