Inventor · disambiguated record
David R. Greenberg
Also filed as: GREENBERG DAVID R · GREENBERG DAVID ROSS
26 granted patents·1 pending application·276 citations·filing 2000–2014
96Inventor score
Top patents by PatentIndex Score
27 records- 0194US9190479B1Transistor structure having an electrical contact structure with multiple metal interconnect levels staggering one anotherINTERNAT BUSINESS MACHINES CPORPORATION·Filed 2014·Granted Nov 17, 2015·19 cites·8 claims
- 0291US8178908B2Electrical contact structure having multiple metal interconnect levels staggering one anotherGREENBERG DAVID ROSS·Filed 2008·Granted May 15, 2012·20 cites·6 claims
- 0388US8872279B2Transistor structure having an electrical contact structure with multiple metal interconnect levels staggering one anotherGREENBERG DAVID R·Filed 2012·Granted Oct 28, 2014·11 cites·5 claims
- 0488US7414275B2Multi-level interconnections for an integrated circuit chipIBM·Filed 2005·Granted Aug 19, 2008·17 cites·8 claims
- 0588US6656809B2Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristicsIBM·Filed 2002·Granted Dec 2, 2003·40 cites·9 claims
- 0686US6426265B1Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technologyIBM·Filed 2001·Granted Jul 30, 2002·25 cites·23 claims
- 0784US7767546B1Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layerIBM·Filed 2009·Granted Aug 3, 2010·12 cites·22 claims
- 0884US7615457B2Method of fabricating self-aligned bipolar transistor having tapered collectorIBM·Filed 2008·Granted Nov 10, 2009·9 cites·8 claims
- 0982US8455924B2Multi-level interconnections for an integrated circuit chipGREENBERG DAVID ROSS·Filed 2008·Granted Jun 4, 2013·11 cites·11 claims
- 1078US8227865B2Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layerDENNARD ROBERT H·Filed 2010·Granted Jul 24, 2012·5 cites·8 claims
- 1176US6787427B2Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristicsIBM·Filed 2003·Granted Sep 7, 2004·17 cites·11 claims
- 1275US6836029B2Micro-electromechanical switch having a conductive compressible electrodeIBM·Filed 2001·Granted Dec 28, 2004·18 cites·15 claims
- 1372US8877606B2Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolationDENNARD ROBERT H·Filed 2012·Granted Nov 4, 2014·2 cites·6 claims
- 1471US7355221B2Field effect transistor having an asymmetrically stressed channel regionIBM·Filed 2005·Granted Apr 8, 2008·3 cites·10 claims
- 1571US7253070B2Transistor structure with minimized parasitics and method of fabricating the sameIBM·Filed 2006·Granted Aug 7, 2007·3 cites·5 claims
- 1670US7425754B2Structure and method of self-aligned bipolar transistor having tapered collectorIBM·Filed 2004·Granted Sep 16, 2008·13 cites·5 claims
- 1767US7075126B2Transistor structure with minimized parasitics and method of fabricating the sameIBM·Filed 2004·Granted Jul 11, 2006·9 cites·5 claims
- 1866US7713829B2Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technologyIBM·Filed 2006·Granted May 11, 2010·1 cites·14 claims
- 1966US7491617B2Transistor structure with minimized parasitics and method of fabricating the sameIBM·Filed 2007·Granted Feb 17, 2009·2 cites·4 claims
- 2063US6429500B1Semiconductor pin diode for high frequency applicationsIBM·Filed 2000·Granted Aug 6, 2002·11 cites·13 claims
- 2161US7642569B2Transistor structure with minimized parasitics and method of fabricating the sameIBM·Filed 2009·Granted Jan 5, 2010·1 cites·4 claims
- 2261US6426547B1Lateral polysilicon pin diode and method for so fabricatingINFORMATION BUSINESS MACHINES·Filed 2000·Granted Jul 30, 2002·13 cites·18 claims
- 2360US6815802B2Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technologyIBM·Filed 2002·Granted Nov 9, 2004·5 cites·5 claims
- 2460US6531720B2Dual sidewall spacer for a self-aligned extrinsic base in SiGe heterojunction bipolar transistorsIBM·Filed 2001·Granted Mar 11, 2003·9 cites·3 claims
- 2555US2010176482A1Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolationIBM·Filed 2009·Application pending·0 cites
- 2646US7173274B2Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technologyIBM·Filed 2004·Granted Feb 6, 2007·0 cites·10 claims
- 2739US8421478B2Radio frequency integrated circuit with on-chip noise source for self-testFLOYD BRIAN ALLAN·Filed 2008·Granted Apr 16, 2013·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →