Inventor · disambiguated record
David W. Hansquine
Also filed as: HANSQUINE DAVID · HANSQUINE DAVID W
14 granted patents·2 pending applications·166 citations·filing 1997–2012
93Inventor score
Top patents by PatentIndex Score
16 records- 0189US8661274B2Temperature compensating adaptive voltage scalers (AVSs), systems, and methodsHANSQUINE DAVID W·Filed 2010·Granted Feb 25, 2014·16 cites·34 claims
- 0282US8750324B2Single wire bus interfaceHANSQUINE DAVID W·Filed 2009·Granted Jun 10, 2014·16 cites·27 claims
- 0380US7184915B2Tiered built-in self-test (BIST) architecture for testing distributed memory modulesQUALCOMM INC·Filed 2003·Granted Feb 27, 2007·30 cites·22 claims
- 0469US7392442B2Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocolQUALCOMM INC·Filed 2003·Granted Jun 24, 2008·15 cites·38 claims
- 0567US7814380B2Built-in self test (BIST) architecture having distributed interpretation and generalized command protocolQUALCOMM INC·Filed 2008·Granted Oct 12, 2010·5 cites·20 claims
- 0663US6757864B1Method and apparatus for efficiently reading and storing state metrics in memory for high-speed ACS viterbi decoder implementationsQUALCOMM INC·Filed 2000·Granted Jun 29, 2004·13 cites·18 claims
- 0760US6205186B1Decoding with partial state information on a convolutionally encoded channelQUALCOMM INC·Filed 1997·Granted Mar 20, 2001·17 cites·30 claims
- 0858US8779824B2Clock distribution using MTJ sensingQUALCOMM INC·Filed 2012·Granted Jul 15, 2014·1 cites·23 claims
- 0958US6333954B1High-speed ACS for Viterbi decoder implementationsQUALCOMM INC·Filed 1999·Granted Dec 25, 2001·20 cites·21 claims
- 1056US6519297B2Decoding with partial state information on a convolutionally encoded channelQUALCOMM INC·Filed 2000·Granted Feb 11, 2003·7 cites·4 claims
- 1142US2005259609A1Single wire bus interfaceHANSQUINE DAVID W·Filed 2004·Application pending·0 cites
- 1237US6366600B1Spreader architecture for direct sequence spread spectrum communicationsQUALCOMM INC·Filed 1998·Granted Apr 2, 2002·9 cites·20 claims
- 1337US6278715B1System and method for reducing deinterleaver memory requirements through chunk allocationQUALCOMM INC·Filed 1998·Granted Aug 21, 2001·6 cites·24 claims
- 1437US2006031618A1Single wire and three wire bus interoperabilityHANSQUINE DAVID W·Filed 2004·Application pending·0 cites
- 1535US6269130B1Cached chainback RAM for serial viterbi decoderQUALCOMM INC·Filed 1998·Granted Jul 31, 2001·5 cites·13 claims
- 1634US6493354B1Resource allocatorQUALCOMM INC·Filed 1998·Granted Dec 10, 2002·6 cites·9 claims
Join the waitlist — get patent alerts
Get an alert when David W. Hansquine files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →