Inventor · disambiguated record
Darren Kerr
Also filed as: KERR DARREN · KERR DARREN R
24 granted patents·1,819 citations·filing 1996–2004
98Inventor score
Top patents by PatentIndex Score
24 records- 0194US6243667B1Network flow switching and flow data exportCISCO SYSTEMS INC·Filed 1996·Granted Jun 5, 2001·292 cites·19 claims
- 0292US7100021B1Barrier synchronization mechanism for processors of a systolic arrayCISCO TECH INC·Filed 2001·Granted Aug 29, 2006·86 cites·80 claims
- 0392US6272621B1Synchronization and control system for an arrayed processing engineCISCO TECH IND·Filed 2000·Granted Aug 7, 2001·71 cites·28 claims
- 0491US6804815B1Sequence control mechanism for enabling out of order context processingCISCO TECH IND·Filed 2000·Granted Oct 12, 2004·89 cites·32 claims
- 0591US6308148B1Network flow data exportCISCO TECH IND·Filed 1996·Granted Oct 23, 2001·205 cites·17 claims
- 0689US7260518B2Network flow switching and flow data reportCISCO TECH INC·Filed 2004·Granted Aug 21, 2007·50 cites·24 claims
- 0789US6442669B2Architecture for a process complex of an arrayed pipelined processing engineCISCO TECH IND·Filed 2000·Granted Aug 27, 2002·52 cites·14 claims
- 0889US6101599ASystem for context switching between processing elements in a pipeline of processing elementsCISCO TECH IND·Filed 1998·Granted Aug 8, 2000·157 cites·16 claims
- 0988US6965615B1Packet striping across a parallel header processorCISCO TECH IND·Filed 2000·Granted Nov 15, 2005·73 cites·5 claims
- 1088US6590894B1Network flow switching and flow data exportCISCO TECH IND·Filed 2000·Granted Jul 8, 2003·48 cites·33 claims
- 1187US6119215ASynchronization and control system for an arrayed processing engineCISCO TECH IND·Filed 1998·Granted Sep 12, 2000·117 cites·20 claims
- 1286US7292578B1Flexible, high performance support for QoS on an arbitrary number of queuesCISCO TECH INC·Filed 2001·Granted Nov 6, 2007·51 cites·17 claims
- 1386US6173386B1Parallel processor with debug capabilityCISCO TECH IND·Filed 1998·Granted Jan 9, 2001·132 cites·12 claims
- 1484US7290105B1Zero overhead resource locks with attributesCISCO TECH INC·Filed 2002·Granted Oct 30, 2007·47 cites·33 claims
- 1584US6195739B1Method and apparatus for passing data among processor complex stages of a pipelined processing engineCISCO TECH IND·Filed 1998·Granted Feb 27, 2001·102 cites·7 claims
- 1681US6513108B1Programmable processing engine for efficiently processing transient dataCISCO TECH IND·Filed 1998·Granted Jan 28, 2003·81 cites·10 claims
- 1775US7475156B2Network flow switching and flow data exportCISCO TECH INC·Filed 2001·Granted Jan 6, 2009·17 cites·16 claims
- 1874US7895412B1Programmable arrayed processing engine architecture for a network switchCISCO TEHNOLOGY INC·Filed 2002·Granted Feb 22, 2011·18 cites·36 claims
- 1969US6836838B1Architecture for a processor complex of an arrayed pipelined processing engineCISCO TECH IND·Filed 2002·Granted Dec 28, 2004·12 cites·23 claims
- 2066US6986022B1Boundary synchronization mechanism for a processor of a systolic arrayCISCO TECH IND·Filed 2001·Granted Jan 10, 2006·11 cites·20 claims
- 2166US6889181B2Network flow switching and flow data exportCISCO TECH IND·Filed 1997·Granted May 3, 2005·45 cites·22 claims
- 2261US7380101B2Architecture for a processor complex of an arrayed pipelined processing engineCISCO TECH INC·Filed 2004·Granted May 27, 2008·6 cites·20 claims
- 2357US6920562B1Tightly coupled software protocol decode with hardware data encryptionCISCO TECH IND·Filed 1998·Granted Jul 19, 2005·36 cites·49 claims
- 2449US7139899B2Selected register decode values for pipeline stage register addressingCISCO TECH INC·Filed 1999·Granted Nov 21, 2006·21 cites·52 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →