Inventor · disambiguated record
Dale Kersten
Also filed as: KERSTEN DALE
12 granted patents·2 pending applications·21 citations·filing 2014–2020
86Inventor score
Files withSANMINA CORP14
Top patents by PatentIndex Score
14 records- 0192US9781830B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2014·Granted Oct 3, 2017·11 cites·13 claims
- 0284US9781844B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2014·Granted Oct 3, 2017·5 cites·20 claims
- 0379US11399439B2Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit boardSANMINA CORP·Filed 2019·Granted Jul 26, 2022·2 cites·4 claims
- 0479US10188001B2Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit boardSANMINA CORP·Filed 2015·Granted Jan 22, 2019·3 cites·13 claims
- 0569US11765827B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2020·Granted Sep 19, 2023·0 cites·8 claims
- 0667US12150254B2Method of forming a laminate structure having a plated through-hole using a removable cover layerSANMINA CORP·Filed 2020·Granted Nov 19, 2024·0 cites·8 claims
- 0760US10362687B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2018·Granted Jul 23, 2019·0 cites·6 claims
- 0859US10757819B2Method of forming a laminate structure having a plated through-hole using a removable cover layerSANMINA CORP·Filed 2014·Granted Aug 25, 2020·0 cites·15 claims
- 0959US10667390B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2017·Granted May 26, 2020·0 cites·9 claims
- 1058US2015181724A1Methods of forming segmented vias for printed circuit boardsSANMINA CORP·Filed 2014·Application pending·0 cites
- 1157US10123432B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2017·Granted Nov 6, 2018·0 cites·14 claims
- 1255US2018317327A1Methods of forming segmented vias for printed circuit boardsSANMINA CORP·Filed 2018·Application pending·0 cites
- 1353US11246226B2Laminate structures with hole plugs and methods of forming laminate structures with hole plugsSANMINA CORP·Filed 2019·Granted Feb 8, 2022·0 cites·14 claims
- 1446US10237983B2Method for forming hole plugSANMINA CORP·Filed 2015·Granted Mar 19, 2019·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →