Inventor · disambiguated record
Dan S. Lavric
Also filed as: LAVRIC DAN · LAVRIC DAN S
11 granted patents·37 pending applications·39 citations·filing 2002–2025
85Inventor score
Top patents by PatentIndex Score
48 records- 0194US11018222B1Metallization in integrated circuit structuresINTEL CORP·Filed 2019·Granted May 25, 2021·16 cites·20 claims
- 0286US12046654B2Integrated circuit structures including a titanium silicide materialINTEL CORP·Filed 2020·Granted Jul 23, 2024·2 cites·17 claims
- 0379US12295170B2Fabrication of gate-all-around integrated circuit structures having additive metal gates and gate dielectrics with a dipole layerINTEL CORP·Filed 2020·Granted May 6, 2025·1 cites·9 claims
- 0477US2024429238A1Fabrication of gate-all-around integrated circuit structures having additive metal gatesINTEL CORP·Filed 2024·Application pending·0 cites
- 0576US2025227992A1Fabrication of gate-all-around integrated circuit structures having additive metal gatesINTEL CORP·Filed 2025·Application pending·0 cites
- 0671US12402387B2Integrated circuit structures including a titanium silicide materialINTEL CORP·Filed 2024·Granted Aug 26, 2025·0 cites·20 claims
- 0769US6846752B2Methods and devices for the suppression of copper hillock formationINTEL CORP·Filed 2003·Granted Jan 25, 2005·17 cites·23 claims
- 0866US2025227960A1Integrated circuit structures having fin isolation regions bound by gate cutsINTEL CORP·Filed 2025·Application pending·0 cites
- 0965US12113068B2Fabrication of gate-all-around integrated circuit structures having additive metal gatesINTEL CORP·Filed 2020·Granted Oct 8, 2024·0 cites·22 claims
- 1060US2024186127A1Sputter targets for self-doped source and drain contactsINTEL CORP·Filed 2023·Application pending·0 cites
- 1159US2024105804A1Integrated circuit structures having fin isolation regions bound by gate cutsINTEL CORP·Filed 2022·Application pending·0 cites
- 1257US2025380494A1Subfin engineering to improve semiconductor device performanceINTEL CORP·Filed 2024·Application pending·0 cites
- 1356US2024312996A1Integrated circuit structures having uniform grid metal gate and trench contact plug for tub gates with pyramidal channel structuresINTEL CORP·Filed 2023·Application pending·0 cites
- 1456US2024321892A1Constrained epitaxial formation using dielectric wallsINTEL CORP·Filed 2023·Application pending·0 cites
- 1555US2025194223A1Uniaxial dual strain in ribbonized channelINTEL CORP·Filed 2023·Application pending·0 cites
- 1654US2025204042A1Backside self-aligned backbone for forksheet transistorsINTEL CORP·Filed 2023·Application pending·0 cites
- 1754US2023420246A1Sputter targets and sources for self-doped source and drain contactsINTEL CORP·Filed 2022·Application pending·0 cites
- 1854US2024312986A1Integrated circuit structures having self-aligned uniform grid metal gate and trench contact plug for tub gatesINTEL CORP·Filed 2023·Application pending·0 cites
- 1954US2024332290A1Transistor with channel-symmetric gateINTEL CORP·Filed 2023·Application pending·0 cites
- 2054US2024213250A1Self-aligned backbone for forksheet transistorsINTEL CORP·Filed 2022·Application pending·0 cites
- 2153US2024204103A1Transistor gate-channel arrangements with multiple dipole materialsINTEL CORP·Filed 2022·Application pending·0 cites
- 2252US12051698B2Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layerINTEL CORP·Filed 2020·Granted Jul 30, 2024·0 cites·23 claims
- 2352US2024006506A1Low-resistance and thermally stable contacts with phosphide or arsenide metal compound layersINTEL CORP·Filed 2022·Application pending·0 cites
- 2451US2024312991A1Fabrication of gate-all-around integrated circuit structures having tuned upper nanowiresINTEL CORP·Filed 2023·Application pending·0 cites
- 2551US2025386533A1Integrated circuit structures having thinned metal gate and trench contact cut plug for tub gatesINTEL CORP·Filed 2024·Application pending·0 cites
- 2650US2024113116A1Epitaxial structure and gate metal structures with a planar top surfaceINTEL CORP·Filed 2022·Application pending·0 cites
- 2750US2024006533A1Low-resistance and thermally stable contacts with boride, indium, or gallium metal compound layersINTEL CORP·Filed 2022·Application pending·0 cites
- 2850US2025098230A1Integrated circuit structures having dual stress gatesINTEL CORP·Filed 2023·Application pending·0 cites
- 2950US2025113598A1Multi-threshold scheme using dual dipole patterning in complementary transistor dielectricsINTEL CORP·Filed 2023·Application pending·0 cites
- 3049US2024105803A1Integrated circuit structures with trench contact depopulation structureINTEL CORP·Filed 2022·Application pending·0 cites
- 3149US2024332394A1Fabrication of gate-all-around integrated circuit structures having multi-layer molybdenum metal gate stackINTEL CORP·Filed 2023·Application pending·0 cites
- 3248US2023317789A1Source or drain structures with selective silicide contacts thereonINTEL CORP·Filed 2022·Application pending·0 cites
- 3348US2025221019A1Integrated circuit structures having uniform grid metal gate and trench contact plug with gate voltage threshold (vt) adjustmentINTEL CORP·Filed 2023·Application pending·0 cites
- 3447US6818548B2Fast ramp anneal for hillock suppression in copper-containing structuresINTEL CORP·Filed 2002·Granted Nov 16, 2004·3 cites·21 claims
- 3547US2023290778A1Fabrication of gate-all-around integrated circuit structures having dual metal gates and gate dielectrics with a single polarity dipole layerINTEL CORP·Filed 2022·Application pending·0 cites
- 3647US2022093596A1Fabrication of gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layerINTEL CORP·Filed 2020·Application pending·0 cites
- 3746US12310060B2Gate-all-around integrated circuit structures having uniform threshold voltages and tight gate endcap tolerancesINTEL CORP·Filed 2021·Granted May 20, 2025·0 cites·20 claims
- 3846US2023209799A1Sram with dipole dopant threshold voltage modulation for greater read stabilityINTEL CORP·Filed 2021·Application pending·0 cites
- 3946US2023275085A1Gate cut grid across integrated circuitINTEL CORP·Filed 2022·Application pending·0 cites
- 4045US2023207704A1Integrated circuits with self-aligned tub architectureLAVRIC DAN S·Filed 2021·Application pending·0 cites
- 4145US2023420531A1Fabrication of gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with an opposite polarity dipole layerINTEL CORP·Filed 2022·Application pending·0 cites
- 4244US2023317807A1Fabrication of gate-all-around integrated circuit structures having additive gate structures in a tub architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 4344US2023290851A1Fabrication of gate-all-around integrated circuit structures having additive gate structuresINTEL CORP·Filed 2022·Application pending·0 cites
- 4443US2011147851A1Method For Depositing Gate Metal For CMOS DevicesTHOMAS CHRISTOPHER D·Filed 2009·Application pending·0 cites
- 4540US11984506B2Field effect transistor having a gate dielectric with a dipole layer and having a gate stressor layerINTEL CORP·Filed 2020·Granted May 14, 2024·0 cites·13 claims
- 4636US11476164B2Integrated circuit structures having differentiated workfunction layersINTEL CORP·Filed 2017·Granted Oct 18, 2022·0 cites·19 claims
- 4735US2019305102A1Cmos device including pmos metal gate with low threshold voltageINTEL CORP·Filed 2018·Application pending·0 cites
- 4834US2019348511A1Cap layer for metal contacts of a semiconductor deviceINTEL CORP·Filed 2017·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Dan S. Lavric files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →