Inventor · disambiguated record
David E. Miner
Also filed as: MINER DAVID · MINER DAVID E
42 granted patents·8 pending applications·438 citations·filing 1999–2015
98Inventor score
Top patents by PatentIndex Score
50 records- 0195US8990505B1Cache memory bank selectionJAMIL SUJAT·Filed 2008·Granted Mar 24, 2015·58 cites·34 claims
- 0292US9058272B1Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addressesMARVELL INT LTD·Filed 2013·Granted Jun 16, 2015·26 cites·17 claims
- 0391US7406553B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2007·Granted Jul 29, 2008·18 cites·20 claims
- 0490US8943273B1Method and apparatus for improving cache efficiencyJAMIL SUJAT·Filed 2009·Granted Jan 27, 2015·31 cites·20 claims
- 0588US8458404B1Programmable cache access protocol to optimize power consumption and performanceDELGROSS JOSEPH·Filed 2009·Granted Jun 4, 2013·24 cites·20 claims
- 0687US8135916B1Method and apparatus for hardware-configurable multi-policy coherence protocolO'BLENESS R FRANK·Filed 2009·Granted Mar 13, 2012·19 cites·11 claims
- 0787US8065576B2Test access portMINER DAVID E·Filed 2009·Granted Nov 22, 2011·16 cites·35 claims
- 0887US6387161B1Nitrous oxide purification system and processAIR LIQUIDE AMERICAN·Filed 2000·Granted May 14, 2002·35 cites·18 claims
- 0986US7404043B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2005·Granted Jul 22, 2008·11 cites·16 claims
- 1081US8631206B1Way-selecting translation lookaside bufferO'BLENESS R FRANK·Filed 2008·Granted Jan 14, 2014·11 cites·11 claims
- 1181US7627797B2Test access portINTEL CORP·Filed 2006·Granted Dec 1, 2009·8 cites·23 claims
- 1278US7139947B2Test access portINTEL CORP·Filed 2000·Granted Nov 21, 2006·20 cites·27 claims
- 1377US8296525B1Method and apparatus for data-less bus queryO'BLENESS FRANK·Filed 2009·Granted Oct 23, 2012·9 cites·20 claims
- 1475US7428607B2Apparatus and method for arbitrating heterogeneous agents in on-chip bussesMARVELL INT LTD·Filed 2006·Granted Sep 23, 2008·5 cites·16 claims
- 1574US7634603B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2008·Granted Dec 15, 2009·4 cites·17 claims
- 1674US6775748B2Methods and apparatus for transferring cache block ownershipINTEL CORP·Filed 2002·Granted Aug 10, 2004·20 cites·31 claims
- 1774US6505482B2Nitrous oxide purification system and processAIR LIQUIDE·Filed 2002·Granted Jan 14, 2003·12 cites·10 claims
- 1873US7062613B2Methods and apparatus for cache interventionINTEL CORP·Filed 2005·Granted Jun 13, 2006·5 cites·38 claims
- 1973US6370911B1Nitrous oxide purification system and processAIR LIQUIDE AMERICAN·Filed 1999·Granted Apr 16, 2002·27 cites·23 claims
- 2072US8688919B1Method and apparatus for associating requests and responses with identification informationMARVELL INT LTD·Filed 2012·Granted Apr 1, 2014·2 cites·20 claims
- 2172US7159077B2Direct processor cache access within a system having a coherent multi-processor protocolINTEL CORP·Filed 2004·Granted Jan 2, 2007·16 cites·30 claims
- 2271US7100001B2Methods and apparatus for cache interventionINTEL CORP·Filed 2002·Granted Aug 29, 2006·16 cites·32 claims
- 2366US6983348B2Methods and apparatus for cache interventionINTEL CORP·Filed 2002·Granted Jan 3, 2006·10 cites·24 claims
- 2464US7219176B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2002·Granted May 15, 2007·6 cites·23 claims
- 2563US7143220B2Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latenciesINTEL CORP·Filed 2004·Granted Nov 28, 2006·6 cites·30 claims
- 2661US7290093B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2003·Granted Oct 30, 2007·5 cites·7 claims
- 2759US8533401B2Implementing direct access caches in coherent multiprocessorsEDIRISOORIYA SAMANTHA J·Filed 2002·Granted Sep 10, 2013·7 cites·4 claims
- 2859US7464227B2Method and apparatus for supporting opportunistic sharing in coherent multiprocessorsINTEL CORP·Filed 2002·Granted Dec 9, 2008·6 cites·27 claims
- 2956US9086976B1Method and apparatus for associating requests and responses with identification informationMARVELL INT LTD·Filed 2014·Granted Jul 21, 2015·0 cites·20 claims
- 3055US8769204B1Programmable cache access protocol to optimize power consumption and performanceMARVELL INT LTD·Filed 2013·Granted Jul 1, 2014·0 cites·20 claims
- 3155US7765349B1Apparatus and method for arbitrating heterogeneous agents in on-chip bussesMARVELL INT LTD·Filed 2008·Granted Jul 27, 2010·0 cites·19 claims
- 3254US7234028B2Power/performance optimized cache using memory write prevention through write snarfingINTEL CORP·Filed 2002·Granted Jun 19, 2007·3 cites·25 claims
- 3352US7640387B2Method and apparatus for implementing heterogeneous interconnectsINTEL CORP·Filed 2008·Granted Dec 29, 2009·0 cites·20 claims
- 3452US7406552B2Systems and methods for early fixed latency subtractive decoding including speculative acknowledgingMARVELL INT LTD·Filed 2007·Granted Jul 29, 2008·0 cites·17 claims
- 3550US9892051B1Method and apparatus for use of a preload instruction to improve efficiency of cacheMARVELL INT LTD·Filed 2015·Granted Feb 13, 2018·0 cites·23 claims
- 3650US7366845B2Pushing of clean data to one or more processors in a system having a coherency protocolINTEL CORP·Filed 2004·Granted Apr 29, 2008·1 cites·38 claims
- 3750US7353317B2Method and apparatus for implementing heterogeneous interconnectsINTEL CORP·Filed 2004·Granted Apr 1, 2008·1 cites·25 claims
- 3849US7487299B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2005·Granted Feb 3, 2009·0 cites·9 claims
- 3948US7966477B1Power optimized replay of blocked operations in a pipilined architectureMARVELL INT LTD·Filed 2010·Granted Jun 21, 2011·0 cites·14 claims
- 4048US7685379B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2005·Granted Mar 23, 2010·0 cites·12 claims
- 4146US7725683B2Apparatus and method for power optimized replay via selective recirculation of instructionsMARVELL INT LTD·Filed 2003·Granted May 25, 2010·0 cites·18 claims
- 4246US2006112238A1Techniques for pushing data to a processor cacheJAMIL SUJAT·Filed 2004·Application pending·0 cites
- 4345US2005125582A1Methods and apparatus to dispatch interrupts in multi-processor systemsFiled 2003·Application pending·0 cites
- 4443US2004111563A1Method and apparatus for cache coherency between heterogeneous agents and limiting data transfers among symmetric processorsFiled 2002·Application pending·0 cites
- 4543US2003195939A1Conditional read and invalidate for use in coherent multiprocessor systemsFiled 2002·Application pending·0 cites
- 4643US2004153611A1Methods and apparatus for detecting an address conflictFiled 2003·Application pending·0 cites
- 4743US2004015669A1Method, system, and apparatus for an efficient cache to support multiple configurationsFiled 2002·Application pending·0 cites
- 4842US2003005380A1Method and apparatus for testing multi-core processorsFiled 2001·Application pending·0 cites
- 4941US7757046B2Method and apparatus for optimizing line writes in cache coherent systemsINTEL CORP·Filed 2002·Granted Jul 13, 2010·0 cites·15 claims
- 5040US2006004965A1Direct processor cache access within a system having a coherent multi-processor protocolTU STEVEN J·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →