Inventor · disambiguated record
David Neto
Also filed as: NETO DAVID
18 granted patents·169 citations·filing 2002–2014
94Inventor score
Top patents by PatentIndex Score
18 records- 0195US7555741B1Computer-aided-design tools for reducing power consumption in programmable logic devicesALTERA CORP·Filed 2006·Granted Jun 30, 2009·50 cites·23 claims
- 0288US7877710B1Method and apparatus for deriving signal activities for power analysis and optimizationALTERA CORP·Filed 2006·Granted Jan 25, 2011·14 cites·29 claims
- 0387US10599404B1M/A for compiling parallel program having barrier synchronization for programmable hardwareNETO DAVID·Filed 2012·Granted Mar 24, 2020·17 cites·27 claims
- 0482US7545196B1Clock distribution for specialized processing block in programmable logic deviceALTERA CORP·Filed 2006·Granted Jun 9, 2009·12 cites·26 claims
- 0581US9697309B1Metastability-hardened synchronization circuitFUNG RYAN·Filed 2009·Granted Jul 4, 2017·10 cites·22 claims
- 0681US8732639B1Method and apparatus for protecting, optimizing, and reporting synchronizersFUNG RYAN·Filed 2009·Granted May 20, 2014·9 cites·37 claims
- 0777US8250500B1Method and apparatus for deriving signal activities for power analysis and optimizationNETO DAVID·Filed 2006·Granted Aug 21, 2012·7 cites·16 claims
- 0877US6957412B1Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elementsALTERA CORP·Filed 2002·Granted Oct 18, 2005·26 cites·35 claims
- 0974US10417362B1Method and apparatus for deriving signal activities for power analysis and optimizationALTERA CORP·Filed 2014·Granted Sep 17, 2019·2 cites·27 claims
- 1071US7774729B1Method and apparatus for reducing dynamic power in a systemALTERA CORP·Filed 2007·Granted Aug 10, 2010·5 cites·24 claims
- 1168US8898603B1Method and apparatus for deriving signal activities for power analysis and optimizationNETO DAVID·Filed 2006·Granted Nov 25, 2014·3 cites·32 claims
- 1268US7587620B1Power reduction techniques for components in integrated circuits by assigning inputs to a plurality of ports based on power consumption ratingsALTERA CORP·Filed 2006·Granted Sep 8, 2009·5 cites·34 claims
- 1366US9342640B1Method and apparatus for protecting, optimizing, and reporting synchronizersALTERA CORP·Filed 2014·Granted May 17, 2016·1 cites·22 claims
- 1463US8001537B1Method and apparatus for compiling programmable logic device configurationsALTERA CORP·Filed 2005·Granted Aug 16, 2011·3 cites·25 claims
- 1559US8499273B1Systems and methods for optimizing placement and routingBOZMAN KIMBERLEY ANNE·Filed 2010·Granted Jul 30, 2013·2 cites·21 claims
- 1650US8015425B1Power reduction techniques for components in integrated circuitsALTERA CORP·Filed 2009·Granted Sep 6, 2011·0 cites·13 claims
- 1749US7877555B1Power-aware RAM processingALTERA CORP·Filed 2006·Granted Jan 25, 2011·2 cites·42 claims
- 1845US9330733B1Power-aware RAM processingTESSIER RUSSELL GEORGE·Filed 2011·Granted May 3, 2016·1 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →