Inventor · disambiguated record
Daniel L. Ostapko
Also filed as: OSTAPKO DANIEL L · OSTAPKO DANIEL LAWRENCE
13 granted patents·166 citations·filing 1974–2008
91Inventor score
Files withIBM13
Top patents by PatentIndex Score
13 records- 0189US6383847B1Partitioned mask layoutIBM·Filed 2000·Granted May 7, 2002·35 cites·17 claims
- 0283US7269817B2Lithographic process window optimization under complex constraints on edge placementIBM·Filed 2004·Granted Sep 11, 2007·23 cites·6 claims
- 0383US3958110ALogic array with testing circuitryIBM·Filed 1974·Granted May 18, 1976·32 cites·7 claims
- 0464US6144224AClock distribution network with dual wire routingIBM·Filed 1999·Granted Nov 7, 2000·20 cites·24 claims
- 0563US7469401B2Method for using partitioned masks to build a chipIBM·Filed 2006·Granted Dec 23, 2008·2 cites·11 claims
- 0651US7870531B2System for using partitioned masks to build a chipIBM·Filed 2008·Granted Jan 11, 2011·0 cites·9 claims
- 0750US7084476B2Integrated circuit logic with self compensating block delaysIBM·Filed 2004·Granted Aug 1, 2006·3 cites·25 claims
- 0850US6430731B1Methods and apparatus for performing slew dependent signal bounding for signal timing analysisIBM·Filed 1999·Granted Aug 6, 2002·24 cites·43 claims
- 0950US4025799ADecoder structure for a folded logic arrayIBM·Filed 1975·Granted May 24, 1977·6 cites·5 claims
- 1046US7302671B2Integrated circuit logic with self compensating shapesIBM·Filed 2005·Granted Nov 27, 2007·0 cites·13 claims
- 1141US5994924AClock distribution network with dual wire routingIBM·Filed 1997·Granted Nov 30, 1999·14 cites·15 claims
- 1235US4029970AChangeable decoder structure for a folded logic arrayIBM·Filed 1975·Granted Jun 14, 1977·3 cites·3 claims
- 1331US4559611AMapping and memory hardware for writing horizontal and vertical linesIBM·Filed 1983·Granted Dec 17, 1985·4 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →