Inventor · disambiguated record
Daniel A. Prener
Also filed as: PRENER DANIEL A · PRENER DANIEL ARTHUR
28 granted patents·2 pending applications·683 citations·filing 1989–2023
96Inventor score
Top patents by PatentIndex Score
30 records- 0193US8949101B2Hardware execution driven application level derating calculation for soft error rate analysisBOSE PRADIP·Filed 2011·Granted Feb 3, 2015·14 cites·25 claims
- 0293US7146607B2Method and system for transparent dynamic optimization in a multiprocessing environmentIBM·Filed 2002·Granted Dec 5, 2006·92 cites·45 claims
- 0393US6560693B1Branch history guided instruction/data prefetchingIBM·Filed 1999·Granted May 6, 2003·221 cites·34 claims
- 0486US7962906B2Compiler method for employing multiple autonomous synergistic processors to simultaneously operate on longer vectors of dataIBM·Filed 2007·Granted Jun 14, 2011·16 cites·9 claims
- 0585US5125092AMethod and apparatus for providing multiple condition code fields to to allow pipelined instructions contention free access to separate condition codesIBM·Filed 1989·Granted Jun 23, 1992·86 cites·8 claims
- 0683US11687369B2Flexible optimized data handling in systems with multiple memoriesIBM·Filed 2021·Granted Jun 27, 2023·1 cites·16 claims
- 0783US7496494B2Method and system for multiprocessor emulation on a multiprocessor host systemIBM·Filed 2002·Granted Feb 24, 2009·31 cites·2 claims
- 0882US8375374B2Partitioning programs between a general purpose core and one or more acceleratorsIBM·Filed 2008·Granted Feb 12, 2013·10 cites·25 claims
- 0975US7441110B1Prefetching using future branch path information derived from branch predictionIBM·Filed 1999·Granted Oct 21, 2008·72 cites·20 claims
- 1074US9632777B2Gather/scatter of multiple data elements with packed loading/storing into/from a register file entryFLEISCHER BRUCE M·Filed 2012·Granted Apr 25, 2017·3 cites·18 claims
- 1173US2023244530A1Flexible optimized data handling in systems with multiple memoriesIBM·Filed 2023·Application pending·0 cites
- 1271US6418525B1Method and apparatus for reducing latency in set-associative caches using set predictionIBM·Filed 1999·Granted Jul 9, 2002·61 cites·12 claims
- 1370US10572263B2Executing a composite VLIW instruction having a scalar atom that indicates an iteration of executionIBM·Filed 2016·Granted Feb 25, 2020·1 cites·21 claims
- 1470US8719548B2Method and system for efficient emulation of multiprocessor address translation on a multiprocessorALTMAN ERIK RICHTER·Filed 2011·Granted May 6, 2014·3 cites·10 claims
- 1570US8108843B2Hybrid mechanism for more efficient emulation and method thereforNAIR RAVI·Filed 2002·Granted Jan 31, 2012·13 cites·23 claims
- 1669US8578351B2Hybrid mechanism for more efficient emulation and method thereforNAIR RAVI·Filed 2011·Granted Nov 5, 2013·2 cites·7 claims
- 1767US10996989B2Flexible optimized data handling in systems with multiple memoriesIBM·Filed 2016·Granted May 4, 2021·1 cites·19 claims
- 1867US7953588B2Method and system for efficient emulation of multiprocessor address translation on a multiprocessor hostIBM·Filed 2002·Granted May 31, 2011·11 cites·31 claims
- 1964US7865699B2Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing codeIBM·Filed 2007·Granted Jan 4, 2011·2 cites·25 claims
- 2061US12182576B2Executing a composite scalar-vector VLIW instruction having a repeat fieldIBM·Filed 2019·Granted Dec 31, 2024·0 cites·19 claims
- 2160US7844446B2Method and system for multiprocessor emulation on a multiprocessor host systemIBM·Filed 2009·Granted Nov 30, 2010·1 cites·17 claims
- 2259US7340588B2Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing codeIBM·Filed 2003·Granted Mar 4, 2008·5 cites·39 claims
- 2358US6032245AMethod and system for interrupt handling in a multi-processor computer system executing speculative instruction threadsIBM·Filed 1997·Granted Feb 29, 2000·34 cites·30 claims
- 2453US9043194B2Method and system for efficient emulation of multiprocessor memory consistencyNAIR RAVI·Filed 2002·Granted May 26, 2015·3 cites·24 claims
- 2553US8972782B2Exposed-pipeline processing element with rollbackIBM·Filed 2012·Granted Mar 3, 2015·0 cites·19 claims
- 2652US9575755B2Vector processing in an active memory deviceFLEISCHER BRUCE M·Filed 2012·Granted Feb 21, 2017·0 cites·19 claims
- 2752US9535694B2Vector processing in an active memory deviceFLEISCHER BRUCE M·Filed 2012·Granted Jan 3, 2017·0 cites·18 claims
- 2851US9632778B2Gather/scatter of multiple data elements with packed loading/storing into /from a register file entryFLEISCHER BRUCE M·Filed 2012·Granted Apr 25, 2017·0 cites·18 claims
- 2943US2006174089A1Method and apparatus for embedding wide instruction words in a fixed-length instruction set architectureIBM·Filed 2005·Application pending·0 cites
- 3042US9038040B2Method for partitioning programs between a general purpose core and one or more acceleratorsO'BRIEN JOHN KEVIN PATRICK·Filed 2006·Granted May 19, 2015·0 cites·27 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →