Inventor · disambiguated record
Dayanand K. Reddy
Also filed as: REDDY DAYANAND K
3 granted patents·84 citations·filing 2000–2001
75Inventor score
Technology areasH03L
Files withLSI LOGIC CORP3
Top patents by PatentIndex Score
3 records- 0183US7042971B1Delay-locked loop with built-in self-test of phase marginLSI LOGIC CORP·Filed 2001·Granted May 9, 2006·37 cites·18 claims
- 0273US6636979B1System for measuring phase error between two clocks by using a plurality of phase latches with different respective delaysLSI LOGIC CORP·Filed 2000·Granted Oct 21, 2003·25 cites·19 claims
- 0372US6262634B1Phase-locked loop with built-in self-test of phase margin and loop gainLSI LOGIC CORP·Filed 2000·Granted Jul 17, 2001·22 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →