Inventor · disambiguated record
David E. Richter
Also filed as: RICHTER DAVID · RICHTER DAVID E
14 granted patents·1,722 citations·filing 1991–1998
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
14 records- 0194US5781750ADual-instruction-set architecture CPU with hidden software emulation modeEXPONENTIAL TECHN INC·Filed 1994·Granted Jul 14, 1998·209 cites·20 claims
- 0294US5481684AEmulating operating system calls in an alternate instruction set using a modified code segment descriptorEXPONENTIAL TECHN INC·Filed 1994·Granted Jan 2, 1996·231 cites·6 claims
- 0392US5481693AShared register architecture for a dual-instruction-set CPUEXPONENTIAL TECHN INC·Filed 1994·Granted Jan 2, 1996·153 cites·7 claims
- 0491US5848264ADebug and video queue for multi-processor chipS3 INC·Filed 1996·Granted Dec 8, 1998·204 cites·20 claims
- 0591US5781457AMerge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALUEXPONENTIAL TECHN INC·Filed 1996·Granted Jul 14, 1998·189 cites·16 claims
- 0687US5455909AMicroprocessor with operation capture facilityCHIPS & TECH INC·Filed 1992·Granted Oct 3, 1995·145 cites·5 claims
- 0785US5440710AEmulation of segment bounds checking using paging with sub-page validityEXPONENTIAL TECHN INC·Filed 1994·Granted Aug 8, 1995·97 cites·25 claims
- 0882US5685009AShared floating-point registers and register port-pairing in a dual-architecture CPUEXPONENTIAL TECHN INC·Filed 1995·Granted Nov 4, 1997·113 cites·19 claims
- 0982US5664159AMethod for emulating multiple debug breakpoints by page partitioning using a single breakpoint registerEXPONENTIAL TECHN INC·Filed 1995·Granted Sep 2, 1997·106 cites·18 claims
- 1076US5652872ATranslator having segment bounds encoding for storage in a TLBEXPONENTIAL TECHN INC·Filed 1995·Granted Jul 29, 1997·81 cites·20 claims
- 1175US6076155AShared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction setsS3 INC·Filed 1998·Granted Jun 13, 2000·73 cites·26 claims
- 1269US5598553AProgram watchpoint checking using paging with sub-page validityEXPONENTIAL TECHN INC·Filed 1995·Granted Jan 28, 1997·49 cites·25 claims
- 1364US5805918ADual-instruction-set CPU having shared register for storing data before switching to the alternate instruction setS3 INC·Filed 1995·Granted Sep 8, 1998·41 cites·9 claims
- 1456US5274791AMicroprocessor with OEM mode for power management with input/output intiated selection of special address spaceCHIPS & TECH INC·Filed 1991·Granted Dec 28, 1993·31 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →