Inventor · disambiguated record
David R. Terry
Also filed as: TERRY DAVID R
48 granted patents·2 pending applications·79 citations·filing 1977–2019
97Inventor score
Top patents by PatentIndex Score
50 records- 0188US9985656B2Generating ECC values for byte-write capable registersIBM·Filed 2015·Granted May 29, 2018·7 cites·6 claims
- 0288US9524171B1Split-level history buffer in a computer processing unitIBM·Filed 2016·Granted Dec 20, 2016·4 cites·1 claims
- 0387US9928128B2In-pipe error scrubbing within a processor coreIBM·Filed 2016·Granted Mar 27, 2018·6 cites·15 claims
- 0487US9740620B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 22, 2017·5 cites·13 claims
- 0586US10073699B2Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architectureIBM·Filed 2015·Granted Sep 11, 2018·5 cites·20 claims
- 0684US9985655B2Generating ECC values for byte-write capable registersIBM·Filed 2015·Granted May 29, 2018·6 cites·11 claims
- 0784US9870045B2Reducing power consumption in a multi-slice computer processorIBM·Filed 2016·Granted Jan 16, 2018·3 cites·7 claims
- 0884US9639418B2Parity protection of a registerIBM·Filed 2015·Granted May 2, 2017·4 cites·20 claims
- 0982US9921833B2Determining of validity of speculative load data after a predetermined period of time in a multi-slice processorIBM·Filed 2015·Granted Mar 20, 2018·3 cites·11 claims
- 1082US9747217B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 29, 2017·3 cites·7 claims
- 1181US10248426B2Direct register restore mechanism for distributed history buffersIBM·Filed 2016·Granted Apr 2, 2019·3 cites·17 claims
- 1277US9959123B2Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessorIBM·Filed 2015·Granted May 1, 2018·2 cites·7 claims
- 1376US10176038B2Partial ECC mechanism for a byte-write capable registerIBM·Filed 2015·Granted Jan 8, 2019·2 cites·20 claims
- 1474US9940139B2Split-level history buffer in a computer processing unitIBM·Filed 2016·Granted Apr 10, 2018·1 cites·1 claims
- 1574US9851979B2Split-level history buffer in a computer processing unitIBM·Filed 2016·Granted Dec 26, 2017·1 cites·1 claims
- 1673US10268482B2Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instructionIBM·Filed 2015·Granted Apr 23, 2019·2 cites·10 claims
- 1772US10379867B2Asynchronous flush and restore of distributed history bufferIBM·Filed 2017·Granted Aug 13, 2019·1 cites·20 claims
- 1871US11163568B2Implementing write ports in register-file array cellIBM·Filed 2018·Granted Nov 2, 2021·1 cites·17 claims
- 1971US10241800B2Split-level history buffer in a computer processing unitIBM·Filed 2015·Granted Mar 26, 2019·1 cites·17 claims
- 2069US10545765B2Multi-level history buffer for transaction memory in a microprocessorIBM·Filed 2017·Granted Jan 28, 2020·1 cites·20 claims
- 2165US10255071B2Method and apparatus for managing a speculative transaction in a processing unitIBM·Filed 2015·Granted Apr 9, 2019·1 cites·20 claims
- 2265US9971604B2History buffer for multiple-field registersIBM·Filed 2015·Granted May 15, 2018·1 cites·20 claims
- 2361US11138050B2Operation of a multi-slice processor implementing a hardware level transfer of an execution threadIBM·Filed 2019·Granted Oct 5, 2021·0 cites·20 claims
- 2460US10564691B2Reducing power consumption in a multi-slice computer processorIBM·Filed 2017·Granted Feb 18, 2020·0 cites·14 claims
- 2560US10209757B2Reducing power consumption in a multi-slice computer processorIBM·Filed 2017·Granted Feb 19, 2019·0 cites·7 claims
- 2660US10140127B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2018·Granted Nov 27, 2018·0 cites·13 claims
- 2760US10127047B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2018·Granted Nov 13, 2018·0 cites·7 claims
- 2858US10671399B2Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor coreIBM·Filed 2017·Granted Jun 2, 2020·0 cites·8 claims
- 2958US4160202AAnalogue automatic voltage controllerDRESSER IND·Filed 1977·Granted Jul 3, 1979·16 cites·4 claims
- 3057US10671398B2Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor coreIBM·Filed 2017·Granted Jun 2, 2020·0 cites·12 claims
- 3156US11093282B2Register file write using pointersIBM·Filed 2019·Granted Aug 17, 2021·0 cites·17 claims
- 3256US9952874B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2016·Granted Apr 24, 2018·0 cites·7 claims
- 3356US9870039B2Reducing power consumption in a multi-slice computer processorIBM·Filed 2015·Granted Jan 16, 2018·0 cites·14 claims
- 3455US9952861B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2015·Granted Apr 24, 2018·0 cites·13 claims
- 3555US9846614B1ECC scrubbing in a multi-slice microprocessorIBM·Filed 2016·Granted Dec 19, 2017·0 cites·20 claims
- 3653US10248421B2Operation of a multi-slice processor with reduced flush and restore latencyIBM·Filed 2016·Granted Apr 2, 2019·0 cites·6 claims
- 3753US10241790B2Operation of a multi-slice processor with reduced flush and restore latencyIBM·Filed 2015·Granted Mar 26, 2019·0 cites·12 claims
- 3852US9928073B2Determining of validity of speculative load data after a predetermined period of time in a multi-slice processorIBM·Filed 2016·Granted Mar 27, 2018·0 cites·6 claims
- 3952US9858078B2Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessorIBM·Filed 2015·Granted Jan 2, 2018·0 cites·13 claims
- 4051US10909034B2Issue queue snooping for asynchronous flush and restore of distributed history bufferIBM·Filed 2017·Granted Feb 2, 2021·0 cites·20 claims
- 4151US10489253B2On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessorIBM·Filed 2017·Granted Nov 26, 2019·0 cites·20 claims
- 4251US10318356B2Operation of a multi-slice processor implementing a hardware level transfer of an execution threadIBM·Filed 2016·Granted Jun 11, 2019·0 cites·12 claims
- 4348US10282205B2Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructionsIBM·Filed 2015·Granted May 7, 2019·0 cites·20 claims
- 4447US10282207B2Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instructionIBM·Filed 2016·Granted May 7, 2019·0 cites·5 claims
- 4547US10223196B2ECC scrubbing method in a multi-slice microprocessorIBM·Filed 2017·Granted Mar 5, 2019·0 cites·18 claims
- 4646US9766975B2Partial ECC handling for a byte-write capable registerIBM·Filed 2015·Granted Sep 19, 2017·0 cites·20 claims
- 4745US10289415B2Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register dataIBM·Filed 2015·Granted May 14, 2019·0 cites·20 claims
- 4844US10296337B2Preventing premature reads from a general purpose registerIBM·Filed 2016·Granted May 21, 2019·0 cites·17 claims
- 4940US2018107510A1Operation of a multi-slice processor implementing instruction fusionIBM·Filed 2016·Application pending·0 cites
- 5038US2017109093A1Method and apparatus for writing a portion of a register in a microprocessorIBM·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →