Inventor · disambiguated record
Daniel J. Vitkavage
Also filed as: VITKAVAGE DANIEL J · VITKAVAGE DANIEL JOSEPH
14 granted patents·1 pending application·693 citations·filing 1990–2002
94Inventor score
Files withAGERE SYST GUARDIAN CORP4LUCENT TECHNOLOGIES INC4AGERE SYSTEMS INC3AT & T BELL LAB2RES TRIANGLE INST1
Top patents by PatentIndex Score
15 records- 0197US5849639AMethod for removing etching residues and contaminantsLUCENT TECHNOLOGIES INC·Filed 1997·Granted Dec 15, 1998·287 cites·17 claims
- 0284US6362638B1Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologiesAGERE SYST GUARDIAN CORP·Filed 1999·Granted Mar 26, 2002·61 cites·18 claims
- 0383US6680542B1Damascene structure having a metal-oxide-metal capacitor associated therewithAGERE SYSTEMS INC·Filed 2000·Granted Jan 20, 2004·38 cites·10 claims
- 0478US5858873AIntegrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereofLUCENT TECHNOLOGIES INC·Filed 1997·Granted Jan 12, 1999·45 cites·7 claims
- 0577US5022958AMethod of etching for integrated circuits with planarized dielectricAT & T BELL LAB·Filed 1990·Granted Jun 11, 1991·68 cites·8 claims
- 0676US5200358AIntegrated circuit with planar dielectric layerAT & T BELL LAB·Filed 1991·Granted Apr 6, 1993·58 cites·5 claims
- 0775US6046115AMethod for removing etching residues and contaminantsLUCENT TECHNOLOGIES INC·Filed 1998·Granted Apr 4, 2000·38 cites·20 claims
- 0872US6028359AIntegrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereforLUCENT TECHNOLOGIES INC·Filed 1998·Granted Feb 22, 2000·34 cites·21 claims
- 0960US6750495B1Damascene capacitors for integrated circuitsAGERE SYSTEMS INC·Filed 1999·Granted Jun 15, 2004·19 cites·7 claims
- 1048US6555910B1Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereofAGERE SYSTEMS INC·Filed 2000·Granted Apr 29, 2003·2 cites·26 claims
- 1147US6280644B1Method of planarizing a surface on an integrated circuitAGERE SYST GUARDIAN CORP·Filed 1999·Granted Aug 28, 2001·13 cites·12 claims
- 1247US5168330ASemiconductor device having a semiconductor substrate interfaced to a dissimilar material by means of a single crystal pseudomorphic interlayerRES TRIANGLE INST·Filed 1990·Granted Dec 1, 1992·11 cites·5 claims
- 1344US6329281B1Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayerAGERE SYST GUARDIAN CORP·Filed 1999·Granted Dec 11, 2001·13 cites·21 claims
- 1440US6384446B2Grooved capacitor structure for integrated circuitsAGERE SYST GUARDIAN CORP·Filed 1998·Granted May 7, 2002·6 cites·9 claims
- 1531US2003218259A1Bond pad support structure for a semiconductor deviceFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →