Inventor · disambiguated record
Dao-Ping Wang
Also filed as: WANG DAO-PING
11 granted patents·121 citations·filing 2006–2022
89Inventor score
Technology areasG11C
Top patents by PatentIndex Score
11 records- 0194US9142285B2Multi-port SRAM with shared write bit-line architecture and selective read path for low power operationUNIV NAT CHIAO TUNG·Filed 2013·Granted Sep 22, 2015·24 cites·9 claims
- 0294US7701755B2Memory having improved power designTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Apr 20, 2010·41 cites·13 claims
- 0385US7468903B2Circuits for improving read and write margins in multi-port SRAMSTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Dec 23, 2008·18 cites·17 claims
- 0481US7505319B2Method and apparatus for high efficiency redundancy scheme for multi-segment SRAMTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Mar 17, 2009·13 cites·31 claims
- 0578US8891289B2Ten-transistor dual-port SRAM with shared bit-line architectureUNIV NAT CHIAO TUNG·Filed 2013·Granted Nov 18, 2014·6 cites·11 claims
- 0677US7420835B2Single-port SRAM with improved read and write marginsTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Sep 2, 2008·10 cites·18 claims
- 0765US7577052B2Power switching circuitTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Aug 18, 2009·6 cites·18 claims
- 0862US12087355B2Adaptive control circuit of static random access memoryMEDIATEK INC·Filed 2022·Granted Sep 10, 2024·0 cites·20 claims
- 0954US7535788B2Dynamic power control for expanding SRAM write marginTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted May 19, 2009·3 cites·13 claims
- 1038US9640229B2Memory circuit and layout structure of a memory circuitMEDIATEK INC·Filed 2015·Granted May 2, 2017·0 cites·15 claims
- 1130US10176853B2Pre-processing circuit with data-line DC immune clamping and associated method and sensing circuitMEDIATEK INC·Filed 2017·Granted Jan 8, 2019·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →