Inventor · disambiguated record
David A. Webber
Also filed as: WEBBER DAVID · WEBBER DAVID A · WEBBER DAVID ALLAN
15 granted patents·438 citations·filing 1997–2013
92Inventor score
Top patents by PatentIndex Score
15 records- 0192US6311313B1X-Y grid tree clock distribution network with tunable tree and grid networksIBM·Filed 1998·Granted Oct 30, 2001·196 cites·28 claims
- 0282US6205571B1X-Y grid tree tuning methodIBM·Filed 1998·Granted Mar 20, 2001·104 cites·18 claims
- 0379US7735051B2Method for replicating and synchronizing a plurality of physical instances with a logical masterIBM·Filed 2006·Granted Jun 8, 2010·10 cites·21 claims
- 0477US5970052AMethod for dynamic bandwidth testingIBM·Filed 1997·Granted Oct 19, 1999·97 cites·13 claims
- 0571US8024647B2Method and system for checking rotate, shift and sign extension functions using a modulo functionIBM·Filed 2008·Granted Sep 20, 2011·4 cites·22 claims
- 0670US7783911B2Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirementsIBM·Filed 2006·Granted Aug 24, 2010·7 cites·9 claims
- 0765US7676776B2Spare gate array cell distribution analysisIBM·Filed 2007·Granted Mar 9, 2010·5 cites·12 claims
- 0863US7734944B2Mechanism for windaging of a double rate driverIBM·Filed 2006·Granted Jun 8, 2010·4 cites·4 claims
- 0960US7376890B2Method and system for checking rotate, shift and sign extension functions using a modulo functionIBM·Filed 2004·Granted May 20, 2008·6 cites·10 claims
- 1055US9075726B2Conflict resolution of cache store and fetch requestsIBM·Filed 2013·Granted Jul 7, 2015·0 cites·10 claims
- 1153US8434051B2Schematic wire annotation toolKOYUNCU KUTALMIS·Filed 2009·Granted Apr 30, 2013·3 cites·20 claims
- 1252US7991816B2Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution unitsIBM·Filed 2008·Granted Aug 2, 2011·0 cites·10 claims
- 1350US9164912B2Conflict resolution of cache store and fetch requestsALEXANDER KHARY J·Filed 2012·Granted Oct 20, 2015·0 cites·8 claims
- 1449US7146520B2Method and apparatus for controlling clocks in a processor with mirrored unitsIBM·Filed 2003·Granted Dec 5, 2006·2 cites·9 claims
- 1546US7509365B2Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution unitsIBM·Filed 2005·Granted Mar 24, 2009·0 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →